16e410669a
List of changes: 1. Add DDR4 and LPDDR4 memory related code - SPD for LPDDR4 - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Fill FSP-M related UPD parameters 3. Add devicetree.cb config parameters related to FSP-M UPD TEST=Able to build and boot ADL-P RVP till ramstage early Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
36 lines
702 B
C
36 lines
702 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <boardid.h>
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#include <ec/acpi/ec.h>
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#include <ec/google/chromeec/ec.h>
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#include <stdint.h>
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#include <types.h>
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#include "board_id.h"
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static uint32_t get_board_id_via_ext_ec(void)
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{
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uint32_t id = BOARD_ID_INIT;
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if (google_chromeec_get_board_version(&id))
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id = BOARD_ID_UNKNOWN;
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return id;
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}
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/* Get Board ID via EC I/O port write/read */
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int get_board_id(void)
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{
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MAYBE_STATIC_NONZERO int id = -1;
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if (id < 0) {
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if (CONFIG(EC_GOOGLE_CHROMEEC)) {
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id = get_board_id_via_ext_ec();
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} else {
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if (send_ec_command(EC_FAB_ID_CMD) == 0) {
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id = recv_ec_data() << 8;
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id |= recv_ec_data();
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}
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}
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}
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return (id & BOARD_ID_MASK);
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}
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