7742aedb0f
Split parameter '(devfn << 2) | intx' to 'devfn, intx'. Formatted with 'spatch --max-width 96' Change-Id: I17a6b3919b6e55aaa7ca2873ca713b36ebe7d3a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55285 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
93 lines
3 KiB
C
93 lines
3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <arch/smp/mpspec.h>
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#include <arch/ioapic.h>
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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struct device *riser = NULL, *firewire = NULL;
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int firewire_bus = 0, riser_bus = 0, isa_bus;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc);
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smp_write_processors(mc);
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firewire = dev_find_device(0x104c, 0x8023, 0);
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if (firewire) {
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firewire_bus = firewire->bus->secondary;
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}
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/* If a riser card is used, this riser is detected on bus 4, so its secondary bus is the */
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/* highest bus number on the pci bus. */
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riser = dev_find_device(0x3388, 0x0021, 0);
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if (!riser)
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riser = dev_find_device(0x3388, 0x0022, 0);
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if (riser) {
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riser_bus = riser->link_list->secondary;
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}
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mptable_write_buses(mc, NULL, &isa_bus);
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/* I/O APICs: APIC ID Version State Address */
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u8 ioapic_id = smp_write_ioapic_from_hw(mc, VIO_APIC_VADDR);
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/* Legacy Interrupts */
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mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
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/* Builtin devices on Bus 0 */
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smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x01, 0, ioapic_id, 0x10);
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smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x02, 0, ioapic_id, 0x10);
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smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1f, 1, ioapic_id, 0x13);
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smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 0, ioapic_id, 0x17);
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smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 1, ioapic_id, 0x13);
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smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 2, ioapic_id, 0x12);
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smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 3, ioapic_id, 0x10);
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smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1b, 0, ioapic_id, 0x10);
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smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1c, 0, ioapic_id, 0x10);
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smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1c, 1, ioapic_id, 0x11);
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/* Internal PCI bus (Firewire, PCI slot) */
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if (firewire) {
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smp_write_pci_intsrc(mc, mp_INT, firewire_bus, 0x00, 0, ioapic_id, 0x10);
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smp_write_pci_intsrc(mc, mp_INT, firewire_bus, 0x01, 0, ioapic_id, 0x14);
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}
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if (riser) {
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/* Old riser card */
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/* riser slot top 5:8.0 */
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smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x08, 0, ioapic_id, 0x14);
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/* riser slot middle 5:9.0 */
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smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x09, 0, ioapic_id, 0x15);
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/* riser slot bottom 5:a.0 */
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smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0a, 0, ioapic_id, 0x16);
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/* New Riser Card */
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smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0c, 0, ioapic_id, 0x14);
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smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0d, 0, ioapic_id, 0x15);
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smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0e, 0, ioapic_id, 0x16);
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}
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/* PCIe slot */
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smp_write_pci_intsrc(mc, mp_INT, 0x1, 0x00, 0, ioapic_id, 0x10);
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smp_write_pci_intsrc(mc, mp_INT, 0x1, 0x00, 1, ioapic_id, 0x11);
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/* Onboard Ethernet */
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smp_write_pci_intsrc(mc, mp_INT, 0x2, 0x00, 0, ioapic_id, 0x10);
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/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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mptable_lintsrc(mc, isa_bus);
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/* Compute the checksums */
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return mptable_finalize(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr, 1);
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return (unsigned long)smp_write_config_table(v);
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}
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