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Paul Menzel 2e585a12a2 sb/amd/cimx/sb800: Get rid of power button device in coreboot 
Apply commit d7b88dcb (mb/google/x86-boards: Get rid of power button
device in coreboot) to AMD Brazos boards [1]:

> As per the ACPI specification, there are two types of power button
> devices:
> 1. Fixed hardware power button
> 2. Generic hardware power button
>
> Fixed hardware power button is added by the OSPM if POWER_BUTTON flag
> is not set in FADT by the BIOS. This device has its programming model
> in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this
> power button device by default if the power button FADT flag is not
> set.
>
> On the other hand, generic hardware power button can be used by
> platforms if fixed register space cannot be used for the power button
> device. In order to support this, power button device object with HID
> PNP0C0C is expected to be added to ACPI tables. Additionally,
> POWER_BUTTON flag should be set to indicate the presence of control
> method for power button.
[..]
> This change gets rid of the generic hardware power button from all
> google mainboards and relies completely on the fixed hardware power
> button.

The same problem exists with the AMD Hudson devices in coreboot.

For AMD Hudson (2) and Yangtze based devices this was removed in commit
44f2fab8 (AMD hudson and yangtze boards: Let mainboard declare power
button) [2].

Two devices are detected.

    $ dmesg | grep Button
    [    0.209213] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0
    [    0.209254] ACPI: Power Button [PWRB]
    [    0.209332] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1
    [    0.209349] ACPI: Power Button [PWRF]

   $ sudo evtest
    No device specified, trying to scan all of /dev/input/event*
    Available devices:
    /dev/input/event0:      Power Button
    /dev/input/event1:      Power Button
    [..]

[1]: https://review.coreboot.org/5546
[2]: https://review.coreboot.org/27272

Change-Id: I0cbecb72f7e1bf3d051d3b7656c6af4d6f43b497
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/27496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 		2019-05-20 14:43:44 +00:00
3rdparty 3rdparty: Uprev vboot submodule to upstream master 2019-05-13 09:32:04 +00:00
Documentation Documentation/lessons: Tidy up lesson 2 2019-05-16 17:45:07 +00:00
configs mb/lenovo/*: Add support for VBOOT on 8MiB devices 2019-05-08 10:31:23 +00:00
payloads libpayload: make log2 and clz work on signed values internally 2019-05-16 20:16:31 +00:00
src sb/amd/cimx/sb800: Get rid of power button device in coreboot 2019-05-20 14:43:44 +00:00
util util/lint/check-style: Don't hardcode clang-format path 2019-05-15 19:46:39 +00:00
.checkpatch.conf .checkpatch.conf: Ignore a few more warnings 2018-08-13 12:23:24 +00:00
.clang-format Revert "lint/clang-format: set to 96 chars per line" 2019-03-15 23:05:06 +00:00
.gitignore util/bucts: Add tool to manipulate BUC.TS bit on Intel targets 2018-11-19 08:19:16 +00:00
.gitmodules 3rdparty/opensbi: Add submodule 2019-04-24 08:46:25 +00:00
.gitreview
…
COPYING
…
MAINTAINERS MAINTAINERS: Update Braswell SoC maintainers 2019-03-06 20:05:11 +00:00
Makefile Hook up Kconfig Ada spec file 2019-02-06 16:20:35 +00:00
Makefile.inc Reland "Makefile.inc: Enable -Wtype-limits"" 2019-05-13 10:25:45 +00:00
README.md README: Convert to Markdown 2018-09-16 13:01:58 +00:00
gnat.adc
…
toolchain.inc arch/power8: Rename to ppc64 2018-11-30 20:02:17 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.