Angel Pons 2e5e99c48c sb/intel/i82801dx: Declare reset register in FADT ... According to Intel Document 290744 (ICH4 datasheet), 0xcf9 is the reset register, and setting bits 1 and 2 will result in a hard reset. Change-Id: Id1a532857d9643d222d61c3902faadd471ae2a9a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>		2020-07-20 13:18:56 +00:00
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acpi	dptf: Fix scope of TCPU device	2020-07-18 16:04:42 +00:00
arch	arch/x86/postcar_loader: Remove unused 'include <cpu/cpu.h>'	2020-07-14 16:15:28 +00:00
commonlib	src: Remove unused 'include <stdint.h>	2020-07-14 16:11:10 +00:00
console	console: Update for vboot before bootblock	2020-06-15 22:07:12 +00:00
cpu	cpu/intel/model_1067x: Drop <cpu/x86/mp.h> include	2020-07-14 16:15:09 +00:00
device	device/xhci: Add helper method to iterate over xhci_supported_protocl	2020-07-12 17:01:24 +00:00
drivers	drivers/intel/dptf: Add missing scope operator around TSR options	2020-07-18 16:04:51 +00:00
ec	ec/google/chromeec: Fix oversights in ec_dptf_helpers	2020-07-18 16:05:33 +00:00
include	dptf: Fix scope of TCPU device	2020-07-18 16:04:42 +00:00
lib	src: Remove unused 'include <types.h>'	2020-07-14 16:10:17 +00:00
mainboard	mb/google/puff: update USB3 gen2 parameters	2020-07-20 12:37:19 +00:00
northbridge	src: Remove unused 'include <cpu/x86/msr.h>'	2020-07-14 16:14:09 +00:00
security	security/vboot: ensure that NVMEM is saved on every kernel space write	2020-07-15 08:42:11 +00:00
soc	amd/{hudson,stoney,picasso}: Drop PM2 settings from FADT	2020-07-20 13:16:46 +00:00
southbridge	sb/intel/i82801dx: Declare reset register in FADT	2020-07-20 13:18:56 +00:00
superio	sio/nuvoton/common/early_serial.c: Guard serial enable	2020-07-19 18:18:12 +00:00
vendorcode	vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3274	2020-07-20 03:59:46 +00:00
Kconfig	arch/x86: Remove RELOCATABLE_RAMSTAGE	2020-07-06 06:17:47 +00:00