Angel Pons a575759c40 sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabled ... Setting registers 64h[19:18] = 2 and 68h[14:13] = 3 enables OBFF, and setting registers 64h[19:18] = 0 and 68h[14:13] = 0 disables OBFF. Register at offset 0x64 is DCAP2, and offset 0x68 is DCTL2. However, current code doesn't account for this. The result is that register 64h[19:18] = 2 and 68h[14:13] = 0, which means the hardware is OBFF-capable but support is disabled, which makes no sense. Given that reference code and Broadwell both disable OBFF, disable it here too. Change-Id: I6c1cafdb435ee22909b077128b3ae5bde5543039 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>		2020-11-07 14:20:38 +00:00
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amd	amdfwtool: Use shell command to get depend file list	2020-11-06 13:06:33 +00:00
intel	sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabled	2020-11-07 14:20:38 +00:00
ricoh/rl5c476	src/southbridge: Drop unneeded empty lines	2020-09-21 16:29:35 +00:00
ti	…