2ed0aa258f
- occured -> occurred - accomodate -> accommodate - existant -> existent - asssertion -> assertion - manangement -> management - cotroller -> controller Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
245 lines
6.4 KiB
C
245 lines
6.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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* Copyright (C) 2008-2009 coresystems GmbH
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* 2012 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H
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#define SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H
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#ifndef __ACPI__
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#ifndef __ASSEMBLER__
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#include "chip.h"
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#endif
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#endif
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#define DEFAULT_TBAR ((u8 *)0xfed1b000)
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#ifndef __ACPI__
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#define DEFAULT_RCBA ((u8 *)0xfed1c000)
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#else
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#define DEFAULT_RCBA 0xfed1c000
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#endif
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#if IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86_Q35)
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/*
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* Qemu has the fw_cfg interface at 0x510. Move the pmbase to a
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* non-conflicting address. No need to worry about speedstep, it
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* is not supported by qemu and isn't enabled in the qemu config.
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*/
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# define DEFAULT_PMBASE 0x00000600
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#else
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# define DEFAULT_PMBASE 0x00000500 /* Speedstep code has this hardcoded, too. */
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#endif
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#define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60)
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#define DEFAULT_GPIOBASE 0x00000580
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#define APM_CNT 0xb2
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#define PM1_STS 0x00
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#define PWRBTN_STS (1 << 8)
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#define RTC_STS (1 << 10)
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#define PM1_EN 0x02
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define PM1_CNT 0x04
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#define SCI_EN (1 << 0)
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#define PM_LV2 0x14
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#define PM_LV3 0x15
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#define PM_LV4 0x16
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#define PM_LV5 0x17
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#define PM_LV6 0x18
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#define GPE0_STS 0x20
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#define SMI_EN 0x30
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#define PERIODIC_EN (1 << 14)
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#define TCO_EN (1 << 13)
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#define APMC_EN (1 << 5)
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#define BIOS_EN (1 << 2)
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#define EOS (1 << 1)
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#define GBL_SMI_EN (1 << 0)
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#define SMI_STS 0x34
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#define ALT_GP_SMI_EN 0x38
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#define ALT_GP_SMI_STS 0x3a
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#define GP_IO_USE_SEL 0x00
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#define GP_IO_SEL 0x04
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#define GP_LVL 0x0c
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#define GPO_BLINK 0x18
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#define GPI_INV 0x2c
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#define GP_IO_USE_SEL2 0x30
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#define GP_IO_SEL2 0x34
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#define GP_LVL2 0x38
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#define DEBUG_PERIODIC_SMIS 0
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#define MAINBOARD_POWER_OFF 0
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#define MAINBOARD_POWER_ON 1
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#define MAINBOARD_POWER_KEEP 2
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#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
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#endif
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/* D31:F0 LPC bridge */
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#define D31F0_PMBASE 0x40
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#define D31F0_ACPI_CNTL 0x44
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#define D31F0_GPIO_BASE 0x48
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#define D31F0_GPIO_CNTL 0x4c
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#define D31F0_PIRQA_ROUT 0x60
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#define D31F0_PIRQB_ROUT 0x61
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#define D31F0_PIRQC_ROUT 0x62
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#define D31F0_PIRQD_ROUT 0x63
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#define D31F0_SERIRQ_CNTL 0x64
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#define D31F0_PIRQE_ROUT 0x68
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#define D31F0_PIRQF_ROUT 0x69
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#define D31F0_PIRQG_ROUT 0x6a
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#define D31F0_PIRQH_ROUT 0x6b
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#define D31F0_LPC_IODEC 0x80
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#define D31F0_LPC_EN 0x82
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#define D31F0_GEN1_DEC 0x84
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#define D31F0_GEN2_DEC 0x88
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#define D31F0_GEN3_DEC 0x8c
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#define D31F0_GEN4_DEC 0x90
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#define D31F0_GEN_PMCON_1 0xa0
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#define D31F0_GEN_PMCON_3 0xa4
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#define D31F0_C5_EXIT_TIMING 0xa8
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#define D31F0_CxSTATE_CNF 0xa9
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#define D31F0_C4TIMING_CNT 0xaa
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#define D31F0_GPIO_ROUT 0xb8
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#define D31F0_RCBA 0xf0
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/* GEN_PMCON_3 bits */
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#define RTC_BATTERY_DEAD (1 << 2)
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#define RTC_POWER_FAILED (1 << 1)
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#define SLEEP_AFTER_POWER_FAIL (1 << 0)
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/* D31:F2 SATA */
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#define D31F2_IDE_TIM_PRI 0x40
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#define D31F2_IDE_TIM_SEC 0x42
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#define D31F2_SIDX 0xa0
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#define D31F2_SDAT 0xa4
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/* D30:F0 PCI-to-PCI bridge */
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#define D30F0_SMLT 0x1b
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/* D28:F0-5 PCIe root ports */
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#define D28Fx_XCAP 0x42
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#define D28Fx_SLCAP 0x54
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#define SMBUS_IO_BASE 0x0400
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/* PCI Configuration Space (D31:F3): SMBus */
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#define SMB_BASE 0x20
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#define HOSTC 0x40
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/* HOSTC bits */
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#define I2C_EN (1 << 2)
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#define SMB_SMI_EN (1 << 1)
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#define HST_EN (1 << 0)
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/* SMBus I/O bits. */
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#define SMBHSTSTAT 0x0
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#define SMBHSTCTL 0x2
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#define SMBHSTCMD 0x3
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#define SMBXMITADD 0x4
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#define SMBHSTDAT0 0x5
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#define SMBHSTDAT1 0x6
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#define SMBBLKDAT 0x7
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#define SMBTRNSADD 0x9
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#define SMBSLVDATA 0xa
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#define SMLINK_PIN_CTL 0xe
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#define SMBUS_PIN_CTL 0xf
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#define SMBUS_TIMEOUT (10 * 1000 * 100)
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#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
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#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
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#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
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#define RCBA_V0CTL 0x0014
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#define RCBA_V1CAP 0x001c
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#define RCBA_V1CTL 0x0020
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#define RCBA_V1STS 0x0026
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#define RCBA_PAT 0x0030
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#define RCBA_ESD 0x0104
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#define RCBA_ULD 0x0110
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#define RCBA_ULBA 0x0118
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#define RCBA_LCAP 0x01a4
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#define RCBA_LCTL 0x01a8
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#define RCBA_LSTS 0x01aa
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#define RCBA_DMIC 0x0234
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#define RCBA_RPFN 0x0238
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#define RCBA_DMC 0x2010
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#define RCBA_HPTC 0x3404
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#define RCBA_BUC 0x3414
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#define RCBA_FD 0x3418 /* Function Disable, see below. */
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#define RCBA_CG 0x341c
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#define RCBA_FDSW 0x3420
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#define RCBA_MAP 0x35f0 /* UHCI controller #6 remapping */
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#define BUC_LAND (1 << 5) /* LAN */
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#define FD_SAD2 (1 << 25) /* SATA #2 */
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#define FD_TTD (1 << 24) /* Thermal Throttle */
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#define FD_PE6D (1 << 21) /* PCIe root port 6 */
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#define FD_PE5D (1 << 20) /* PCIe root port 5 */
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#define FD_PE4D (1 << 19) /* PCIe root port 4 */
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#define FD_PE3D (1 << 18) /* PCIe root port 3 */
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#define FD_PE2D (1 << 17) /* PCIe root port 2 */
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#define FD_PE1D (1 << 16) /* PCIe root port 1 */
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#define FD_EHCI1D (1 << 15) /* EHCI #1 */
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#define FD_LBD (1 << 14) /* LPC bridge */
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#define FD_EHCI2D (1 << 13) /* EHCI #2 */
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#define FD_U5D (1 << 12) /* UHCI #5 */
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#define FD_U4D (1 << 11) /* UHCI #4 */
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#define FD_U3D (1 << 10) /* UHCI #3 */
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#define FD_U2D (1 << 9) /* UHCI #2 */
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#define FD_U1D (1 << 8) /* UHCI #1 */
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#define FD_U6D (1 << 7) /* UHCI #6 */
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#define FD_HDAD (1 << 4) /* HD audio */
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#define FD_SD (1 << 3) /* SMBus */
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#define FD_SAD1 (1 << 2) /* SATA #1 */
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#define SKPAD_ACPI_S3_MAGIC 0xcafed00d
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#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe
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#ifndef __ACPI__
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#ifndef __ASSEMBLER__
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static inline int lpc_is_mobile(const u16 devid)
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{
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return (devid == 0x2917) || (devid == 0x2919);
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}
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#define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID))
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#if defined(__PRE_RAM__)
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void enable_smbus(void);
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int smbus_read_byte(unsigned device, unsigned address);
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void i82801ix_early_init(void);
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void i82801ix_dmi_setup(void);
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void i82801ix_dmi_poll_vc1(void);
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#endif
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#endif
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#endif
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#endif
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