6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
53 lines
1.2 KiB
C
53 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#define __SIMPLE_DEVICE__
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#include <arch/romstage.h>
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#include <device/pci_ops.h>
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#include <cbmem.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <program_loading.h>
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#include <cpu/intel/smm_reloc.h>
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#include "ironlake.h"
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static uintptr_t smm_region_start(void)
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{
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/* Base of TSEG is top of usable DRAM */
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uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
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return tom;
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}
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static uintptr_t northbridge_get_tseg_base(void)
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{
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return smm_region_start();
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}
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static size_t northbridge_get_tseg_size(void)
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{
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return CONFIG_SMM_TSEG_SIZE;
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}
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void *cbmem_top_chipset(void)
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{
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return (void *) smm_region_start();
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}
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void smm_region(uintptr_t *start, size_t *size)
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{
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*start = northbridge_get_tseg_base();
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*size = northbridge_get_tseg_size();
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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{
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uintptr_t top_of_ram;
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/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
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* above top of the ram. This satisfies MTRR alignment requirement
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* with different TSEG size configurations.
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*/
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top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
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postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
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}
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