coreboot-kgpe-d16/src/soc/intel
Wim Vervoorn 30e9149c4f soc/intel/common/block/smbus: Use i2c read eeprom to speedup SPD read
Reading the SPD using the SMBUS routines takes a long time because each
byte or word is access seperately.

Allow using the i2c read eeprom routines to read the SPD. By doing this
the start address is only sent once per page.

The time required to read a DDR4 SPD is reduced from 200 msec to 50
msec.

BUG=N/A
TEST=tested on facebook monolith

Change-Id: I44e18b8ba72e1b2321f83402a6a055e2be6f940c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-05-18 07:11:24 +00:00
..
apollolake soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size() 2020-05-14 15:06:39 +00:00
baytrail src: Remove unused '#include <stdint.h>' 2020-05-13 08:48:17 +00:00
braswell src: Remove unused '#include <stdint.h>' 2020-05-13 08:48:17 +00:00
broadwell src: Remove unused '#include <stddef.h>' 2020-05-13 08:48:50 +00:00
cannonlake src: Remove leading blank lines from SPDX header 2020-05-18 07:00:27 +00:00
common soc/intel/common/block/smbus: Use i2c read eeprom to speedup SPD read 2020-05-18 07:11:24 +00:00
denverton_ns src: Remove leading blank lines from SPDX header 2020-05-18 07:00:27 +00:00
icelake src: Remove leading blank lines from SPDX header 2020-05-18 07:00:27 +00:00
jasperlake jasperlake: update processor power limits configuration 2020-05-18 07:10:13 +00:00
quark src: Remove leading blank lines from SPDX header 2020-05-18 07:00:27 +00:00
skylake soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size() 2020-05-14 15:06:39 +00:00
tigerlake soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method 2020-05-18 07:07:03 +00:00
xeon_sp src: Remove leading blank lines from SPDX header 2020-05-18 07:00:27 +00:00
Kconfig fsp2_0: Gather Kconfig declarations 2020-04-05 23:26:24 +00:00