Martin Roth 31f7a726ff soc/amd/cezanne: save chipset state to CBMEM ... Guybrush complains that this is missing during the boot, so add it to cezanne. I verified that the registers in gpio.c are correct. BUG=b:184549804 TEST=Build and boot Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3de3764c99fe89b962db88065575463b365ddaf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2021-04-14 00:00:51 +00:00
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acpi	soc/amd/cezanne: Comment the AOAC register access	2021-03-30 23:04:34 +00:00
include/soc	soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSP	2021-04-07 22:49:08 +00:00
acpi.c	soc/amd/cezanne/acpi: Generate MADT LAPIC NMI settings	2021-02-26 23:45:22 +00:00
aoac.c	soc/amd/cezanne: add AOAC support	2021-01-14 15:42:34 +00:00
bootblock.c	soc/amd/cezanne/bootblock: call write_resume_eip in bootblock_c_entry	2021-02-13 17:09:11 +00:00
chip.c	soc/amd/cezanne: Add device tree support for I2C	2021-04-01 15:40:36 +00:00
chip.h	soc/amd/cezanne: Get I2C specific code for cezanne	2021-03-22 03:43:25 +00:00
chipset.cb	soc/amd/cezanne: Add i2c controllers to chipset.cb	2021-03-15 01:15:13 +00:00
config.c
cpu.c	soc/amd: move warm reset flag function prototypes to common code	2021-03-11 15:11:20 +00:00
data_fabric.c	soc/amd/cezanne/data_fabric: add ACPI names and SSDT entries	2021-02-16 00:08:06 +00:00
early_fch.c	soc/amd/cezanne: Set Power state after power failure	2021-04-10 20:22:54 +00:00
fch.c	soc/amd/cezanne: Initialize I2C	2021-03-22 03:44:30 +00:00
fsp_m_params.c	soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSP	2021-04-07 22:49:08 +00:00
fsp_s_params.c	vc/amd/fsp/cezanne: update UPD headers	2021-04-07 22:48:43 +00:00
fw.cfg	soc/amd/cezanne: Add PSP whitelist debug unlock support	2021-03-01 08:27:57 +00:00
gpio.c	soc/amd: remove special GPIO_2 override soc_gpio_hook	2021-04-08 16:47:27 +00:00
i2c.c	soc/amd/cezanne: Get I2C specific code for cezanne	2021-03-22 03:43:25 +00:00
Kconfig	soc/amd/cezanne: save chipset state to CBMEM	2021-04-14 00:00:51 +00:00
Makefile.inc	soc/amd/cezanne: factor out UPD-M configuration from romstage	2021-03-29 19:52:22 +00:00
pcie_gpp.c	soc/amd/cezanne/pci_gpp: Add ACPI names for GPP bridges	2021-03-18 02:33:28 +00:00
reset.c	soc/amd: move warm reset flag function prototypes to common code	2021-03-11 15:11:20 +00:00
romstage.c	soc/amd/cezanne: save chipset state to CBMEM	2021-04-14 00:00:51 +00:00
root_complex.c	soc/amd/cezanne/acpi: Add pci0.asl	2021-02-22 07:29:31 +00:00
smihandler.c	soc/amd/cezanne/smihandler: add ELOG and SMMSTORE support	2021-03-10 00:30:15 +00:00
smu.c	soc/amd/cezanne: add SMU support	2021-03-04 19:55:27 +00:00
uart.c	soc/amd/cezanne/uart: write ACPI tables	2021-02-17 10:35:26 +00:00
xhci.c	soc/amd/cezanne: add XHCI SCI/GEVENT setup	2021-03-12 20:31:55 +00:00