coreboot-kgpe-d16/src/southbridge/amd
Uwe Hermann 3335adb771 This is a full rewrite of all the CS5530/CS5530A code. The previous code was
mostly undocumented, had a broken coding style, contained lots of dead
code and had several other problems, e.g. it enabled write access to the
ROM (why?), it unconditionally enabled primary/secondary IDE (which should
have a config option) and that even _twice_ (which is um... wrong).

The new code

 - has 'ide0_enable' and 'ide1_enable' config options (which actually
   work) to enable/disable the primary/secondary IDE interface in
   Config.lb.

 - Does _not_ enable write access to the ROM (or is there some good
   reason to do that? If so, it should at least have a config option).

 - Contains a bit more documentation.

 - Uses readable (and documented) #defines instead of hardcoded magic values.

 - aaand... it actually compiles ;-) Yep, that's right. The previous code
   wouldn't even build, as it hadn't been fully ported from v1 (still used
   v1 functions which are simply not available in v2).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-14 00:09:29 +00:00
..
amd8111 Use the canonical name of the vendors/devices and the 2006-11-05 18:50:49 +00:00
amd8131 eric patch 2005-07-08 02:49:49 +00:00
amd8131-disable eric patch 2005-07-08 02:49:49 +00:00
amd8132 - Apply 11_24_a_s1_core.diff from 2005-11-26 16:56:05 +00:00
amd8151 S2885 winbond Superio all resource set 2004-10-27 00:37:30 +00:00
cs5530 This is a full rewrite of all the CS5530/CS5530A code. The previous code was 2007-09-14 00:09:29 +00:00
cs5535 more 5536 -> 5536 conversion 2006-04-20 22:54:32 +00:00
cs5536 The GPIOs used for UART2 RX and TX were reversed. 2007-06-19 22:07:16 +00:00