Saurabh Mishra debb8085c6 vc/intel/fsp: Update ADL N FSP headers from v3222.03 to v3267.01 ... Update generated FSP headers for Alder Lake N from v3222.03 to v3267.01. Changes include: - Add UPD Lp5BankMode - Update UPD Offset in FspmUpd.h BUG=b:240373012 BRANCH=None TEST=Build using "emerge-nissa intel-adlnfsp"and boot Nissa. Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Change-Id: I7b921e2aa467593a1c764fc554e2e83e8bb522e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66222 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2022-08-07 19:39:43 +00:00
..
amd	Revert "UPSTREAM: soc/amd/sabrina,vc/amd/fsp/sabrina: Add UART support for Sabrina"	2022-08-01 12:36:31 +00:00
cavium	rules.h: Use more consistent naming	2022-05-16 21:52:22 +00:00
eltan	vc/eltan/security/verified_boot/Makefile: add fmap_config.h dependency	2022-02-22 15:56:03 +00:00
google	util/elogtool: Mark redundant boot mode event type as deprecated	2022-08-06 14:06:33 +00:00
intel	vc/intel/fsp: Update ADL N FSP headers from v3222.03 to v3267.01	2022-08-07 19:39:43 +00:00
mediatek	mb/google: Replace some strings in regulator.c	2022-07-21 10:30:57 +00:00
siemens
Makefile.inc