Maulik V Vaghela 351f1e68c4 soc/intel/alderlake: Update CPU and IGD Device IDs ... Updated CPU ID and IGD ID for Alder Lake as per EDS. TEST=Code compilation works and coreboot is able to boot and identify new device Ids. Change-Id: I2759a41a0db1eba5d159edfc89460992914fcc3c Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-05-14 09:03:01 +00:00
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acpi	soc/intel/alderlake: Skip D3Cold for TBT	2021-04-10 12:00:33 +00:00
bootblock	soc/intel/alderlake: Update CPU and IGD Device IDs	2021-05-14 09:03:01 +00:00
include/soc	soc/intel/alderlake: Add known CPU Port IDs for GPIO communities	2021-05-14 08:57:57 +00:00
romstage	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
spd	util: Add new memory part to LP4x list	2021-03-03 15:50:47 +00:00
acpi.c	soc/intel/alderlake: Use device ID from pci_devs header file	2021-04-26 08:27:54 +00:00
chip.c	soc/intel: Replace open-coded buffer length calculation	2021-04-21 14:21:44 +00:00
chip.h	soc/intel/alderlake: remove duplicate PL2 override	2021-05-04 15:03:44 +00:00
chipset.cb	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
cpu.c	soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT	2021-05-07 06:05:37 +00:00
crashlog.c	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
dptf.c	soc/intel/alderlake: Add DPTF HIDs for Alder Lake SoC	2021-04-23 14:46:33 +00:00
elog.c	soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros	2021-05-03 16:28:53 +00:00
espi.c	src: Match array format in function declarations and definitions	2021-05-13 18:34:38 +00:00
finalize.c
fsp_params.c	soc/intel/alderlake: Allow devicetree to fill UPD related to TCSS OC	2021-04-16 06:44:28 +00:00
gpio.c	soc/intel/alderlake: Add known GPIO virtual wire information	2021-05-14 08:58:07 +00:00
gspi.c
i2c.c
Kconfig	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
lockdown.c
Makefile.inc	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
me.c
meminit.c	soc/intel/adl: Allow mainboard to fill CmdMirror and DqDqsRetraining	2021-05-10 06:40:37 +00:00
p2sb.c
pcie_rp.c	soc/intel/alderlake: Update PCH and CPU PCIe RP table	2021-01-18 07:28:51 +00:00
pmc.c	soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT	2021-05-07 06:05:37 +00:00
pmutil.c	soc/intel/*/pmutil.c: Align cosmetics across platforms	2021-02-24 11:34:42 +00:00
reset.c
smihandler.c	soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster	2021-05-07 06:05:18 +00:00
soundwire.c
spi.c	soc/intel/alderlake: Add SPI DMI Destination ID	2020-12-23 03:28:47 +00:00
systemagent.c	soc/intel/alderlake: add processor power limits control support	2021-03-28 16:08:02 +00:00
uart.c	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00
xhci.c	soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support	2021-02-24 11:27:51 +00:00