4c7979a241
This does the following: - select MAINBOARD_USES_FSP2_0 on Kabylake (does not support FSP1.1) - Remove stale Kconfig option on intel/saddlebrook - select SOC_INTEL_KABYLAKE on intel/kblrvp Change-Id: I64f48eeb00150aea039d533b0ac471fdd8483b90 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
111 lines
2.9 KiB
Makefile
111 lines
2.9 KiB
Makefile
ifeq ($(CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE),y)
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subdirs-y += nhlt
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subdirs-y += romstage
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subdirs-y += ../../../cpu/intel/common
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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bootblock-y += bootblock/bootblock.c
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bootblock-$(CONFIG_FSP_CAR) += fspcar.c
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bootblock-y += bootblock/cpu.c
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bootblock-y += i2c.c
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bootblock-y += bootblock/pch.c
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bootblock-y += bootblock/report_platform.c
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bootblock-y += gpio.c
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bootblock-y += gspi.c
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bootblock-y += p2sb.c
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bootblock-y += pmutil.c
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bootblock-y += spi.c
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bootblock-y += lpc.c
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bootblock-y += uart.c
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verstage-y += gspi.c
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verstage-y += pmutil.c
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verstage-y += i2c.c
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verstage-y += spi.c
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verstage-y += uart.c
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romstage-y += gpio.c
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romstage-y += gspi.c
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romstage-y += i2c.c
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romstage-y += memmap.c
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romstage-y += me.c
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romstage-y += pmc.c
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romstage-y += pmutil.c
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romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
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romstage-y += spi.c
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romstage-y += uart.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += chip_fsp20.c
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ramstage-y += cpu.c
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ramstage-y += elog.c
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ramstage-y += finalize.c
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ramstage-y += gpio.c
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ramstage-y += gspi.c
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ramstage-y += i2c.c
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ramstage-y += graphics.c
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ramstage-y += irq.c
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ramstage-y += lockdown.c
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ramstage-y += lpc.c
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ramstage-y += me.c
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ramstage-y += memmap.c
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ramstage-y += p2sb.c
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ramstage-y += pmc.c
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ramstage-y += pmutil.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
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ramstage-y += sd.c
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ramstage-y += smmrelocate.c
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ramstage-y += spi.c
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ramstage-y += systemagent.c
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ramstage-y += thermal.c
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ramstage-y += uart.c
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ramstage-y += vr_config.c
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smm-y += elog.c
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smm-y += gpio.c
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smm-y += p2sb.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-y += uart.c
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postcar-y += memmap.c
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postcar-y += gspi.c
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postcar-y += spi.c
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postcar-y += i2c.c
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postcar-y += uart.c
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ifeq ($(CONFIG_SKYLAKE_SOC_PCH_H),y)
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# Skylake H Q0
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_506ex/microcode.bin
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# Kabylake HB0
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_906ex/microcode.bin
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else
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# Skylake D0
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_406ex/microcode.bin
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# Kabylake H0, Y0
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_806ex/microcode.bin
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endif
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# Missing for Skylake C0 (0x406e2), Kabylake G0 (0x406e8), Kabylake HA0 (0x506e8)
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# since those are probably pre-release samples.
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CPPFLAGS_common += -I$(src)/soc/intel/skylake
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CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
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ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y)
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CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp11
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CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake
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else
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CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20
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endif
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# Currently used for microcode path.
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CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR)
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endif
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