Lubomir Rintel 38d1eb4403 northbridge/via/cn700/acpi: Add the host bridge ... Includes the DRAM controller device that knows which where the division between addresses routed to the main memory and to the PCI bus is. Change-Id: Id4cfeb8ff32de37723eee68a61c576e657dad30b Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18896 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>		2017-04-14 17:20:06 +02:00
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acpi	src/acpi: Capitalize ACPI and SATA	2016-07-31 19:25:40 +02:00
arch	arch/x86: remove CAR global migration when postcar stage is used	2017-04-08 23:22:02 +02:00
commonlib	commonlib: Wrap lines at 80 columns	2017-03-13 21:23:21 +01:00
console	console: Enable do_printk_va_list for VBOOT	2016-12-27 18:07:39 +01:00
cpu	arch/x86: remove CAR global migration when postcar stage is used	2017-04-08 23:22:02 +02:00
device	libgfxinit: Select CONFIG_VGA when needed	2017-04-08 13:03:52 +02:00
drivers	drivers/spi/tpm: Clean up SPI TPM driver	2017-04-13 05:04:13 +02:00
ec	ec/roda/it8518: Do EC write manually with long timeout	2017-04-08 13:17:56 +02:00
include	drivers/spi/tpm: Clean up SPI TPM driver	2017-04-13 05:04:13 +02:00
lib	src/lib/jpeg: Fix missing closing brace	2017-03-29 13:05:18 +02:00
mainboard	mainboard/google/eve: Remove ACPI ALS device	2017-04-14 04:21:52 +02:00
northbridge	northbridge/via/cn700/acpi: Add the host bridge	2017-04-14 17:20:06 +02:00
soc	soc/intel/apollolake: Change IOSF_BASE_ADDRESS to PCR_BASE_ADDRESS	2017-04-13 22:16:21 +02:00
southbridge	amd/pi/hudson: Add SERIRQ setup	2017-04-14 17:09:27 +02:00
superio	superio/fintek: Add support for Fintek F71808A	2017-03-27 19:19:56 +02:00
vboot	Remove libverstage as separate library and source file class	2017-03-28 22:18:53 +02:00
vendorcode	AGESA f14: Fix memory clock register decoding	2017-04-08 15:19:09 +02:00
Kconfig	GDB_WAIT: Clarify Kconfig description	2017-03-14 22:20:47 +01:00