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coreboot-kgpe-d16/src/mainboard/supermicro/h8dmr_fam10
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Kyösti Mälkki 20c294884f amdfam10 boards: Simplify early resourcemap 
Purpose of the table is to load initial address maps
on PCI function 0:18.1. Provide a macro of its own so
it is clear no other PCI devfn is accessed here.

Change-Id: Ic146207580a5625c4f6799693157b02422bef00a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10 13:40:40 +00:00
..
board_info.txt
cmos.layout mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
devicetree.cb src: Get rid of unneeded whitespace 2018-06-14 09:32:34 +00:00
get_bus_conf.c amdfam10 boards: Use defaults for get_pci1234() 2019-01-04 17:23:56 +00:00
hda_verb.c src/mainboard: Add and update license headers 2018-06-02 21:00:10 +00:00
irq_tables.c amdfam10 boards: Use PCI_DEVFN() 2019-01-09 12:44:11 +00:00
Kconfig mb/*/*/Kconfig: Remove useless comment 2018-11-28 13:53:51 +00:00
Kconfig.name kconfig: automatically include mainboards 2015-04-18 08:31:08 +02:00
Makefile.inc amdfam10 boards: Add Makefiles and fix resourcemap.c 2019-01-04 17:20:08 +00:00
mb_sysconf.h tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
mptable.c amdfam10 boards: Use smp_write_pci_intsrc() 2019-01-09 12:44:52 +00:00
README Use more secure HTTPS URLs for coreboot sites 2017-06-07 12:04:50 +02:00
resourcemap.c amdfam10 boards: Simplify early resourcemap 2019-01-10 13:40:40 +00:00
romstage.c mb: Move timestamp_add_now to northbridge/amd/amdfam10 2019-01-10 03:14:49 +00:00

README 


There are a number of outstanding issues:

* I'm seeing toolchain issues. I can't get this tree to compile correctly with
gcc 4.3 (32 bit) - there is an optimization issue where certain parts of the
CBFS code execute very slowly. With gcc 3.4 (32 bit) that slowness
disappears. This is probably not a problem related to this port specifically.

* setting CONFIG_DEFAULT_CONSOLE_LOGLEVEL lower than 8 simply hangs the boot
shortly after the warm reset triggered by the MCP55 code. I think this too
might be a toolchain problem (but I see it on gcc 3.4 as well as 4.3).

* during startup, the CPU cores talk through each other on serial for a
while. Again, not an issue specific to this port.

* to avoid very slow LZMA decompression I use this port with LZMA compression
disabled in CBFS. I'm not sure what's causing this particular slowness.

See also this thread: https://www.coreboot.org/pipermail/coreboot/2009-September/052107.html

Ward, 2009-09-22