57afc5e0f2
The VA space needs to be extended to support 48bit, as on Cavium SoCs the MMIO starts at 1 << 47. The following changes were done to coreboot and libpayload: * Use page table lvl 0 * Increase VA bits to 48 * Enable 256TB in MMU controller * Add additional asserts Tested on Cavium SoC and two ARM64 Chromebooks. Change-Id: I89e6a4809b6b725c3945bad7fce82b0dfee7c262 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/24970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> |
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| .. | ||
| lib | ||
| Kconfig | ||
| Makefile.inc | ||
| cache.c | ||
| coreboot.c | ||
| cpu.S | ||
| dummy_media.c | ||
| exception.c | ||
| exception_asm.S | ||
| gdb.c | ||
| head.S | ||
| libpayload.ldscript | ||
| main.c | ||
| memcpy.S | ||
| memmove.S | ||
| memset.S | ||
| mmu.c | ||
| selfboot.c | ||
| sysinfo.c | ||
| timer.c | ||
| util.S | ||
| virtual.c | ||