f5116952bb
Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. To make the SOC behavior consistent the XdciEnable config option is removed in favor of direct control by devicetree.cb and the mainboards that had defined it were adjusted accordingly. This was tested on an Eve board with xDCI enabled in devicetree.cb to ensure the xDCI device is enabled in developer mode and disabled in normal mode. Change-Id: Ic3c84beac87452f17490de32082030880834501d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25365 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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| .. | ||
| acpi | ||
| spd | ||
| acpi_tables.c | ||
| board_info.txt | ||
| bootblock.c | ||
| chromeos.c | ||
| chromeos.fmd | ||
| devicetree.cb | ||
| dsdt.asl | ||
| ec.c | ||
| ec.h | ||
| gpio.h | ||
| Kconfig | ||
| Kconfig.name | ||
| mainboard.c | ||
| Makefile.inc | ||
| ramstage.c | ||
| romstage.c | ||
| smihandler.c | ||