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coreboot-kgpe-d16/Documentation/mainboard/intel/kblrvp11.md
Jonathan Neuschäfer a2faaa9a27 Documentation/mb/intel/kblrvp11: Fix table formatting 
Without this patch, Sphinx 1.7.9 prints the following warning, and
doesn't emit the table as HTML:

  /.../Documentation/mainboard/intel/kblrvp11.md:1: WARNING: Malformed table.

  +------------------+---------------------------------------------------+
  | CPU              | Kaby lake H (i7-7820EQ)                          |
  +------------------+---------------------------------------------------+
  | PCH              | Skylake PCH-H (called SPT-H)                      |
  +------------------+---------------------------------------------------+
  | Coprocessor      | Intel ME                                          |
  +------------------+---------------------------------------------------+

Change-Id: I17920398126d57eb8815c45e4a0d4b100f46004a
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-20 14:20:49 +00:00

2.3 KiB
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Intel Kaby lake RVP11

Specs

  • 1 SATA cable connect
  • 1 SATAe direct
  • 2 USB2.0 connector
  • 4 USB3.0 connector
  • 1 Gigabit Ethernet
  • 1 x4 PCIe slot
  • 1 x1 PCIe slot
  • 1 X16 PEG slot
  • UART debug DB9 connector
  • 4 DIMMS with DDR4 memory
  • SPI flash
  • Audio Jack
  • PS2 Keyboard and Mouse
  • Display: HDMI, DP, VGA

Target Audience

  • OEMs, internal only

Flashing coreboot

+---------------------+------------+
| Type                | Value      |
+=====================+============+
| Socketed flash      | no         |
+---------------------+------------+
| Vendor              | Winbond    |
+---------------------+------------+
| Model               | W25Q128FV  |
+---------------------+------------+
| Size                | 16 MiB     |
+---------------------+------------+
| Package             | SOIC-8     |
+---------------------+------------+
| Write protection    | No         |
+---------------------+------------+
| Dual BIOS feature   | No         |
+---------------------+------------+

Instruction to flash coreboot to SPI

Internal programming

The SPI flash can be accessed internally using flashrom. The following command is used to flash BIOS region.

$ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all

External programming

  1. Dediprog SF600 with adapter B is used.
  2. Make sure power supply is disconnected from board.
  3. Connect Dediprog SF600 to header at J7H1.
  4. Ensure that "currently working on" is in "application memory chip 1"
  5. Go to "file" and select the .rom file (16 MB) to program chip1.
  6. Execute the batch operation to erase and program the chip.

Technology

+------------------+---------------------------------------------------+
| CPU              | Kaby lake H (i7-7820EQ)                           |
+------------------+---------------------------------------------------+
| PCH              | Skylake PCH-H (called SPT-H)                      |
+------------------+---------------------------------------------------+
| Coprocessor      | Intel ME                                          |
+------------------+---------------------------------------------------+