4aff4458f5
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
39 lines
1.2 KiB
Text
39 lines
1.2 KiB
Text
chip northbridge/intel/sch
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device lapic_cluster 0 on
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chip cpu/intel/socket_441
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device lapic 0 on end
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end
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end
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device domain 0 on
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device pci 00.0 on end # host bridge
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device pci 02.0 on end # Integrated Graphics and Video Device
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chip southbridge/intel/sch
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register "pirqa_routing" = "0xa"
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register "pirqb_routing" = "0xb"
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register "pirqc_routing" = "0x5"
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register "pirqd_routing" = "0xf"
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register "pirqe_routing" = "0x80"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x80"
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device pci 1a.0 on end # 26 0 USB Client
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device pci 1b.0 on end # 27 0 HD Audio Controller
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device pci 1c.0 on end # 28 0 PCI Express Port 1
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device pci 1c.1 on end # 28 1 PCI Express Port 2
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device pci 1d.0 on end # USB Classic UHCI Controller 1
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device pci 1d.1 on end # USB Classic UHCI Controller 2
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device pci 1d.2 on end # USB Classic UHCI Controller 3
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device pci 1d.7 on end # USB2 EHCI Controller
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device pci 1e.0 on end # SDIO/MMC Port 0
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device pci 1e.1 on end # SDIO/MMC Port 1
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device pci 1e.2 on end # SDIO/MMC Port 2
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device pci 1f.0 on end # LPC bridge
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device pci 1f.1 on end # PATA Controller
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end
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end
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end
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