58d3fce181
Change-Id: I6a066659758aeb0251d9b37f525ad987b90832db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41787 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
31 lines
870 B
C
31 lines
870 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/romstage.h>
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#include <cbmem.h>
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#include <cpu/x86/mtrr.h>
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#include <soc/reg_access.h>
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void fill_postcar_frame(struct postcar_frame *pcf)
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{
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uintptr_t top_of_ram;
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uintptr_t top_of_low_usable_memory;
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/* Locate the top of RAM */
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top_of_low_usable_memory = (uintptr_t) cbmem_top();
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top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB);
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/* Cache postcar and ramstage */
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postcar_frame_add_mtrr(pcf, top_of_ram - (16 * MiB), 16 * MiB,
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MTRR_TYPE_WRBACK);
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/* Cache RMU area */
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postcar_frame_add_mtrr(pcf, (uintptr_t) top_of_low_usable_memory,
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0x10000, MTRR_TYPE_WRTHROUGH);
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/* Cache ESRAM */
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postcar_frame_add_mtrr(pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);
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pcf->skip_common_mtrr = 1;
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/* Cache SPI flash - Write protect not supported */
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postcar_frame_add_romcache(pcf, MTRR_TYPE_WRTHROUGH);
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}
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