coreboot-kgpe-d16/src/soc
Marshall Dawson 39a4ac1502 soc/amd/picasso: Update southbridge
Picasso's FCH has many similarities to Stoney Ridge, so few changes
are necessary.  The most notable changes are:
 * Update the index values for the C00/C01 interrupt routing
 * FORCE_STPCLK_RETRY is not present
 * PCIB is not defined
 * FCH MISC Registers 0xfed80e00 numbering has changed
 * C-state base moves from PM register to MSR
 * Add option to determine the intended MUX settion for LPC vs. eMMC
 * Remove the LEGACY_FREE option

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I69dfc4a875006639aa330385680d150331840e40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20 16:31:54 +00:00
..
amd soc/amd/picasso: Update southbridge 2019-10-20 16:31:54 +00:00
cavium devicetree: Fix improper use of chip_operations 2019-10-04 16:29:31 +00:00
imgtec cpu,mb,soc: Init missing lb_serial struct fields 2019-09-19 09:28:10 +00:00
intel soc/intel/common: lpc/espi: fix wrong lock bit 2019-10-18 14:55:35 +00:00
mediatek soc/mediatek/mt8183: Compress calibration blob with LZ4 2019-10-18 12:25:23 +00:00
nvidia cpu,mb,soc: Init missing lb_serial struct fields 2019-09-19 09:28:10 +00:00
qualcomm soc/qualcomm: Remove default ops to generate bootblock.bin 2019-10-09 22:24:56 +00:00
rockchip arm64: Uprev Arm TF and adjust to BL31 parameter changes 2019-09-14 05:01:16 +00:00
samsung cpu,mb,soc: Init missing lb_serial struct fields 2019-09-19 09:28:10 +00:00
sifive soc/sifive/fu540: test and fix code of fu540 spi 2019-10-16 14:12:20 +00:00
ucb lib: Rewrite qemu-armv7 ramdetect 2019-07-28 11:31:42 +00:00