3a54318856
The EM100Pro allows the debug console to be sent over the SPI bus. This is not yet working in romstage due to the use of static variables in the SPI driver code. It is also not working on chipsets that have SPI write buffers of less than 10 characters due to the 9 byte command/header length specified by the EM100 protocol. While this currently works only with the EM100, it seems like it would be useful on any logic analyzer with SPI debug - just filter on command bytes of 0x11. Change-Id: Icd42ccd96cab0a10a4e70f4b02ecf9de8169564b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
353 lines
9 KiB
Text
353 lines
9 KiB
Text
menu "Console"
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config BOOTBLOCK_CONSOLE
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bool "Enable early (bootblock) console output."
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depends on ARCH_ARM || ARCH_RISCV || ARCH_MIPS
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default n
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help
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Use console during the bootblock if supported
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config SQUELCH_EARLY_SMP
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bool "Squelch AP CPUs from early console."
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default y
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help
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When selected only the BSP CPU will output to early console.
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Console drivers have unpredictable behaviour if multiple threads
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attempt to share the same resources without a spinlock.
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If unsure, say Y.
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config CONSOLE_SERIAL
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bool "Serial port console output"
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default y
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depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL
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help
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Send coreboot debug output to a serial port.
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The type of serial port driver selected based on your configuration is
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shown on the following menu line. Supporting multiple different types
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of UARTs in one build is not supported.
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if CONSOLE_SERIAL
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comment "I/O mapped, 8250-compatible"
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depends on DRIVERS_UART_8250IO
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comment "memory mapped, 8250-compatible"
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depends on DRIVERS_UART_8250MEM
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comment "device-specific UART"
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depends on HAVE_UART_SPECIAL
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config UART_FOR_CONSOLE
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int "Index for UART port to use for console"
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default 0
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# FIXME: Early programming in romstage is incorrect as we should
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# program different LDN to actually change the physical port.
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config TTYS0_BASE
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hex
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depends on DRIVERS_UART
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default 0x3f8 if UART_FOR_CONSOLE = 0
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default 0x2f8 if UART_FOR_CONSOLE = 1
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default 0x3e8 if UART_FOR_CONSOLE = 2
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default 0x2e8 if UART_FOR_CONSOLE = 3
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help
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Map the COM port number to the respective I/O port.
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choice
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prompt "Baud rate"
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default CONSOLE_SERIAL_115200
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config CONSOLE_SERIAL_115200
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bool "115200"
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help
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Set serial port Baud rate to 115200.
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config CONSOLE_SERIAL_57600
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bool "57600"
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help
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Set serial port Baud rate to 57600.
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config CONSOLE_SERIAL_38400
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bool "38400"
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help
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Set serial port Baud rate to 38400.
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config CONSOLE_SERIAL_19200
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bool "19200"
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help
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Set serial port Baud rate to 19200.
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config CONSOLE_SERIAL_9600
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bool "9600"
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help
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Set serial port Baud rate to 9600.
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endchoice
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#FIXME(dhendrix): Change name to SERIAL_BAUD? (Stefan sayz: yes!!)
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config TTYS0_BAUD
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int
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default 115200 if CONSOLE_SERIAL_115200
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default 57600 if CONSOLE_SERIAL_57600
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default 38400 if CONSOLE_SERIAL_38400
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default 19200 if CONSOLE_SERIAL_19200
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default 9600 if CONSOLE_SERIAL_9600
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help
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Map the Baud rates to an integer.
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# TODO: Allow user-friendly selection of settings other than 8n1.
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config TTYS0_LCS
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int
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default 3
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depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM
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endif # CONSOLE_SERIAL
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config SPKMODEM
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bool "spkmodem (console on speaker) console output"
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default n
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help
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Send coreboot debug output through speaker
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config CONSOLE_USB
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bool "USB dongle console output"
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depends on USBDEBUG
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default n
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help
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Send coreboot debug output to USB.
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Configuration for USB hardware is under menu Generic Drivers.
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# TODO: Deps?
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# TODO: Improve description.
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config ONBOARD_VGA_IS_PRIMARY
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bool "Use onboard VGA as primary video device"
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default n
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help
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If not selected, the last adapter found will be used.
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config CONSOLE_NE2K
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bool "Network console over NE2000 compatible Ethernet adapter"
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default n
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help
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Send coreboot debug output to a Ethernet console, it works
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same way as Linux netconsole, packets are received to UDP
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port 6666 on IP/MAC specified with options bellow.
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Use following netcat command: nc -u -l -p 6666
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config CONSOLE_NE2K_DST_MAC
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depends on CONSOLE_NE2K
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string "Destination MAC address of remote system"
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default "00:13:d4:76:a2:ac"
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help
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Type in either MAC address of logging system or MAC address
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of the router.
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config CONSOLE_NE2K_DST_IP
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depends on CONSOLE_NE2K
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string "Destination IP of logging system"
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default "10.0.1.27"
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help
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This is IP address of the system running for example
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netcat command to dump the packets.
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config CONSOLE_NE2K_SRC_IP
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depends on CONSOLE_NE2K
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string "IP address of coreboot system"
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default "10.0.1.253"
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help
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This is the IP of the coreboot system
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config CONSOLE_NE2K_IO_PORT
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depends on CONSOLE_NE2K
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hex "NE2000 adapter fixed IO port address"
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default 0xe00
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help
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This is the IO port address for the IO port
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on the card, please select some non-conflicting region,
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32 bytes of IO spaces will be used (and align on 32 bytes
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boundary, qemu needs broader align)
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config CONSOLE_CBMEM
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bool "Send console output to a CBMEM buffer"
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default y
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help
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Enable this to save the console output in a CBMEM buffer. This would
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allow to see coreboot console output from Linux space.
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if CONSOLE_CBMEM
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config CONSOLE_CBMEM_BUFFER_SIZE
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hex "Room allocated for console output in CBMEM"
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default 0x20000
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help
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Space allocated for console output storage in CBMEM. The default
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value (128K or 0x20000 bytes) is large enough to accommodate
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even the BIOS_SPEW level.
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config CONSOLE_CBMEM_DUMP_TO_UART
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depends on !CONSOLE_SERIAL
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bool "Dump CBMEM console on resets"
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default n
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help
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Enable this to have CBMEM console buffer contents dumped on the
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serial output in case serial console is disabled and the device
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resets itself while trying to boot the payload.
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endif
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config CONSOLE_QEMU_DEBUGCON
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bool "QEMU debug console output"
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depends on BOARD_EMULATION_QEMU_X86
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default y
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help
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Send coreboot debug output to QEMU's isa-debugcon device:
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qemu-system-x86_64 \
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-chardev file,id=debugcon,path=/dir/file.log \
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-device isa-debugcon,iobase=0x402,chardev=debugcon
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config CONSOLE_QEMU_DEBUGCON_PORT
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hex "QEMU debug console port"
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depends on CONSOLE_QEMU_DEBUGCON
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default 0x402
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config SPI_CONSOLE
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bool "SPI debug console output"
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depends on HAVE_SPI_CONSOLE_SUPPORT && !DEBUG_SPI_FLASH
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help
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Enable support for the debug console on the Dediprog EM100Pro.
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This is currently working only in ramstage due to how the spi
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drivers are written.
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choice
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prompt "Default console log level"
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default DEFAULT_CONSOLE_LOGLEVEL_8
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config DEFAULT_CONSOLE_LOGLEVEL_8
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bool "8: SPEW"
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help
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Way too many details.
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config DEFAULT_CONSOLE_LOGLEVEL_7
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bool "7: DEBUG"
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help
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Debug-level messages.
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config DEFAULT_CONSOLE_LOGLEVEL_6
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bool "6: INFO"
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help
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Informational messages.
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config DEFAULT_CONSOLE_LOGLEVEL_5
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bool "5: NOTICE"
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help
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Normal but significant conditions.
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config DEFAULT_CONSOLE_LOGLEVEL_4
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bool "4: WARNING"
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help
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Warning conditions.
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config DEFAULT_CONSOLE_LOGLEVEL_3
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bool "3: ERR"
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help
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Error conditions.
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config DEFAULT_CONSOLE_LOGLEVEL_2
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bool "2: CRIT"
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help
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Critical conditions.
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config DEFAULT_CONSOLE_LOGLEVEL_1
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bool "1: ALERT"
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help
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Action must be taken immediately.
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config DEFAULT_CONSOLE_LOGLEVEL_0
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bool "0: EMERG"
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help
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System is unusable.
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endchoice
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config DEFAULT_CONSOLE_LOGLEVEL
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int
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default 0 if DEFAULT_CONSOLE_LOGLEVEL_0
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default 1 if DEFAULT_CONSOLE_LOGLEVEL_1
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default 2 if DEFAULT_CONSOLE_LOGLEVEL_2
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default 3 if DEFAULT_CONSOLE_LOGLEVEL_3
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default 4 if DEFAULT_CONSOLE_LOGLEVEL_4
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default 5 if DEFAULT_CONSOLE_LOGLEVEL_5
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default 6 if DEFAULT_CONSOLE_LOGLEVEL_6
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default 7 if DEFAULT_CONSOLE_LOGLEVEL_7
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default 8 if DEFAULT_CONSOLE_LOGLEVEL_8
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help
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Map the log level config names to an integer.
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config NO_POST
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bool "Don't show any POST codes"
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default n
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config CMOS_POST
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bool "Store post codes in CMOS for debugging"
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depends on !NO_POST && PC80_SYSTEM
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default n
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help
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If enabled, coreboot will store post codes in CMOS and switch between
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two offsets on each boot so the last post code in the previous boot
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can be retrieved. This uses 3 bytes of CMOS.
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config CMOS_POST_OFFSET
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hex "Offset into CMOS to store POST codes"
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depends on CMOS_POST
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default 0
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help
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If CMOS_POST is enabled then an offset into CMOS must be provided.
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If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value
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defined in the mainboard option table.
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config CMOS_POST_EXTRA
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bool "Store extra logging info into CMOS"
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depends on CMOS_POST
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default n
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help
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This will enable extra logging of work that happens between post
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codes into CMOS for debug. This uses an additional 8 bytes of CMOS.
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config CONSOLE_POST
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bool "Show POST codes on the debug console"
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depends on !NO_POST
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default n
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help
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If enabled, coreboot will additionally print POST codes (which are
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usually displayed using a so-called "POST card" ISA/PCI/PCI-E
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device) on the debug console.
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config POST_DEVICE
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bool "Send POST codes to an external device"
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depends on !NO_POST
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default y
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choice
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prompt "Device to send POST codes to"
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depends on POST_DEVICE
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default POST_DEVICE_NONE
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config POST_DEVICE_NONE
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bool "None"
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config POST_DEVICE_LPC
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bool "LPC"
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config POST_DEVICE_PCI_PCIE
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bool "PCI/PCIe"
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endchoice
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config POST_IO
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bool "Send POST codes to an IO port"
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depends on PC80_SYSTEM && !NO_POST
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default y
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help
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If enabled, POST codes will be written to an IO port.
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config POST_IO_PORT
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depends on POST_IO
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hex "IO port for POST codes"
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default 0x80
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help
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POST codes on x86 are typically written to the LPC bus on port
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0x80. However, it may be desirable to change the port number
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depending on the presence of coprocessors/microcontrollers or if the
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platform does not support IO in the conventional x86 manner.
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endmenu
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