3a54318856
The EM100Pro allows the debug console to be sent over the SPI bus. This is not yet working in romstage due to the use of static variables in the SPI driver code. It is also not working on chipsets that have SPI write buffers of less than 10 characters due to the 9 byte command/header length specified by the EM100 protocol. While this currently works only with the EM100, it seems like it would be useful on any logic analyzer with SPI debug - just filter on command bytes of 0x11. Change-Id: Icd42ccd96cab0a10a4e70f4b02ecf9de8169564b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
147 lines
3.4 KiB
Text
147 lines
3.4 KiB
Text
config SOC_INTEL_BRASWELL
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bool
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help
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Braswell M/D part support.
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if SOC_INTEL_BRASWELL
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_RAMSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_VERSTAGE_X86_32
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select BACKUP_DEFAULT_SMM_REGION
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select CACHE_MRC_SETTINGS
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
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select COLLECT_TIMESTAMPS
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select SUPPORT_CPU_UCODE_IN_CBFS
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select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
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select HAS_PRECBMEM_TIMESTAMP_REGION
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select HAVE_MONOTONIC_TIMER
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select HAVE_SMI_HANDLER
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select HAVE_HARD_RESET
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select MMCONF_SUPPORT
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select MMCONF_SUPPORT_DEFAULT
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select RELOCATABLE_MODULES
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select PARALLEL_MP
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select PCIEXP_ASPM
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select PCIEXP_CLK_PM
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select PCIEXP_COMMON_CLOCK
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select PCIEXP_L1_SUB_STATE
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select PLATFORM_USES_FSP1_1
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select REG_SCRIPT
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_FSP_RAM_INIT
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select SOC_INTEL_COMMON_FSP_ROMSTAGE
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_COMMON_STACK
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select SOC_INTEL_COMMON_STAGE_CACHE
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select SMM_TSEG
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select SMP
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select SPI_FLASH
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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select TSC_CONSTANT_RATE
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select TSC_MONOTONIC_TIMER
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select TSC_SYNC_MFENCE
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select UDELAY_TSC
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select USE_GENERIC_FSP_CAR_INC
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select HAVE_INTEL_FIRMWARE
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select HAVE_SPI_CONSOLE_SUPPORT
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config BOOTBLOCK_CPU_INIT
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string
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default "soc/intel/braswell/bootblock/bootblock.c"
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config MMCONF_BASE_ADDRESS
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hex "PCIe CFG Base Address"
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default 0xe0000000
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config MAX_CPUS
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int
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default 4
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config CPU_ADDR_BITS
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int
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default 36
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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# Cache As RAM region layout:
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#
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# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE
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# | Stack |\
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# | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE
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# | v |/
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# +-------------+
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# | ^ |
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# | | |
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# | CAR Globals |
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# +-------------+ DCACHE_RAM_BASE
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#
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config DCACHE_RAM_BASE
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hex "Temporary RAM Base Address"
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default 0xfef00000
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config DCACHE_RAM_SIZE
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hex "Temporary RAM Size"
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default 0x4000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
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must add up to a power of 2.
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config DCACHE_RAM_ROMSTAGE_STACK_SIZE
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hex
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default 0x800
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help
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The amount of anticipated stack usage from the data cache
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during pre-ram rom stage execution.
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config RESET_ON_INVALID_RAMSTAGE_CACHE
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bool "Reset the system on S3 wake when ramstage cache invalid."
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default n
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depends on RELOCATABLE_RAMSTAGE
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help
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The haswell romstage code caches the loaded ramstage program
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in SMM space. On S3 wake the romstage will copy over a fresh
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ramstage that was cached in the SMM space. This option determines
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the action to take when the ramstage cache is invalid. If selected
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the system will reset otherwise the ramstage will be reloaded from
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cbfs.
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config ENABLE_BUILTIN_COM1
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bool "Enable builtin COM1 Serial Port"
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default n
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help
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The PMC has a legacy COM1 serial port. Choose this option to
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configure the pads and enable it. This serial port can be used for
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the debug console.
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config HAVE_IFD_BIN
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def_bool y
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config BUILD_WITH_FAKE_IFD
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def_bool !HAVE_IFD_BIN
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config HAVE_ME_BIN
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def_bool y
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config IED_REGION_SIZE
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hex
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default 0x400000
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config CHIPSET_BOOTBLOCK_INCLUDE
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string
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default "soc/intel/braswell/bootblock/timestamp.inc"
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endif
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