a5cdf75f69
Even though the implementation is different on Stoneyridge compared to Picasso and Cezanne, the function prototypes are identical, so move them to the AMD SoC common reset header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
42 lines
798 B
C
42 lines
798 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/io.h>
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#include <cf9_reset.h>
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#include <reset.h>
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#include <soc/southbridge.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/reset.h>
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void set_warm_reset_flag(void)
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{
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uint8_t ncp = inw(NCP_ERR);
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outb(NCP_ERR, ncp | NCP_WARM_BOOT);
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}
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int is_warm_reset(void)
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{
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return !!(inb(NCP_ERR) & NCP_WARM_BOOT);
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}
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void do_cold_reset(void)
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{
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/* De-assert and then assert all PwrGood signals on CF9 reset. */
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pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
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TOGGLE_ALL_PWR_GOOD);
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outb(RST_CPU | SYS_RST, RST_CNT);
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}
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void do_warm_reset(void)
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{
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set_warm_reset_flag();
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/* Assert reset signals only. */
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outb(RST_CPU | SYS_RST, RST_CNT);
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}
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void do_board_reset(void)
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{
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/* TODO: Would a warm_reset() suffice? */
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do_cold_reset();
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}
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