Raul E Rangel 3acc515bef soc/amd/{cezanne,common}: Enable IOMMU PCIe Device ... This change only enables the IOMMU device. We still require the IVRS table to take advantage of the IOMMU. This will happen when the picasso IVRS code is moved into common. BUG=b:190515051 TEST=lspci shows IOMMU device 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>		2021-07-12 12:30:33 +00:00
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cezanne	soc/amd/{cezanne,common}: Enable IOMMU PCIe Device	2021-07-12 12:30:33 +00:00
common	soc/amd/{cezanne,common}: Enable IOMMU PCIe Device	2021-07-12 12:30:33 +00:00
picasso	soc/amd/picasso,stoneyridge/mca: remove unneeded line break	2021-07-12 04:30:39 +00:00
stoneyridge	soc/amd/picasso,stoneyridge/mca: remove unneeded line break	2021-07-12 04:30:39 +00:00
Kconfig	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00