Furquan Shaikh 3bfe3404df intel/skylake: Add support to enable wake-on-usb attach/detach ... Three things are required to enable wake-on-usb: 1. 5V to USB ports should be enabled in S3. 2. ASL file needs to have appropriate wake bit set. 3. XHCI controller should have the wake on attach/detach bit set for the corresponding port in PORTSCN register. Only part missing was #3. This CL adds support to allow mainboard to define a bitmap in devicetree corresponding to the ports that it wants to enable wake-on-usb feature. Based on the bitmap, wake on attach/detach bits in PORTSCN would be set by xhci.asl for the appropriate ports. BUG=chrome-os-partner:58734 BRANCH=None TEST=Verified that with port 5 enabled, chell wakes up from S3 on usb attach/detach. Change-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17056 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2016-10-26 08:33:37 +02:00
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apollolake	soc/intel/apollolake: Enable write-protect SPI flash range support	2016-10-26 01:51:00 +02:00
baytrail
braswell
broadwell	intel/broadwell: "free" memory after use	2016-10-19 21:26:49 +02:00
common	soc/intel/common: Enable support to write protect SPI flash range	2016-10-26 01:50:36 +02:00
fsp_baytrail
fsp_broadwell_de	soc/intel/fsp_broadwell_de: Fix system hang when timestamp is enabled	2016-10-09 19:08:07 +02:00
quark
sch
skylake	intel/skylake: Add support to enable wake-on-usb attach/detach	2016-10-26 08:33:37 +02:00