coreboot-kgpe-d16/src/soc
Rizwan Qureshi 1222a73205 skylake: Add initial FSP2.0 support
Add Initial pieces of code to support fsp2.0 in skylake keeping
the fsp1.1 flow intact.

The soc/romstage.h and soc/ramstage.h have a reference to
fsp driver includes, so split these header files for
each version of FSP driver.

Add the below files,
car_stage.S:
	Add romstage entry point (car_stage_entry).
	This calls into romstage_fsp20.c and aslo handles
	the car teardown.
romstage_fsp20.c:
	Call fsp_memory_init() and also has the callback
	for filling memory init parameters.

Also add monotonic_timer.c to verstage.

With this patchset and relevant change in kunimitsu mainboard,
we are able to boot to romstage.

TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1
Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0

Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16267
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-08-31 20:02:07 +02:00
..
broadcom/cygnus src/soc: Remove unnecessary whitespace before "\n" and "\t" 2016-08-28 18:25:14 +02:00
dmp/vortex86ex src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-07-31 19:27:53 +02:00
imgtec/pistachio drivers/uart: Use uart_platform_refclk for all UART models 2016-05-09 18:45:44 +02:00
intel skylake: Add initial FSP2.0 support 2016-08-31 20:02:07 +02:00
marvell src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-07-31 19:27:53 +02:00
mediatek/mt8173 src/soc: Remove unnecessary whitespace before "\n" and "\t" 2016-08-28 18:25:14 +02:00
nvidia chromeos: Make CHROMEOS_RAMOOPS_NON_ACPI a default for non-ACPI boards 2016-08-13 23:23:16 +02:00
qualcomm soc/qualcomm/ipq40xx: Reduce the delay in I2C. 2016-08-11 22:30:34 +02:00
rdc/r8610 rdc/r8610: Move to src/soc 2016-05-05 20:08:58 +02:00
rockchip rockchip/rk3399: Move romstage.c to mainboard/gru 2016-08-31 19:59:55 +02:00
samsung src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-07-31 19:27:53 +02:00
ucb/riscv soc/ucb/riscv: select BOOTBLOCK_CONSOLE 2016-08-15 18:24:42 +02:00