3d523635e8
All SPI interface setup related functionality that Stoneyridge implemented in its southbridge code is already present in the common AMD SoC code, so use that code instead. The common fch_spi_early_init function requires the SPI controller's base address to be set, so call lpc_set_spibase(SPI_BASE_ADDRESS) right before it. fch_spi_early_init then calls lpc_enable_spi_rom and lpc_enable_spi_prefetch which can be removed from the board code now. Next it calls fch_spi_configure_4dw_burst which does the same as the now removed sb_disable_4dw_burst function when SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST is set to n which is the default. This option can also only be set to y for SoCs that aren't Stoneyridge. Finally fch_spi_early_init calls fch_spi_config_modes which configures the SPI mode and speed settings according to the Kconfig settings and the settings in the amdfw part. On Kahlee this was done by calls to sb_read_mode and sb_set_spi100 before. The previous patch added the remaining Kconfig settings, so the resulting register values don't change in the non-EM100 case. In the EM100 case the TPM speed is changed from 64 to 16 MHz. TEST=Both the non-EM100 mode with a real SPI flash and the EM100 mode with a first-generation EM100 results in Google/Barla reaching the payload and the show_spi_speeds_and_modes call in bootblock prints the expected settings: relevant bootblock console output in non-EM100 case: SPI normal read speed: 33.33 MHz SPI fast read speed: 66.66 Mhz SPI alt read speed: 66.66 Mhz SPI TPM read speed: 66.66 Mhz SPI100: Enabled SPI Read Mode: Dual IO (1-2-2) relevant bootblock console output in EM100 case: SPI normal read speed: 16.66 MHz SPI fast read speed: 16.66 MHz SPI alt read speed: 16.66 MHz SPI TPM read speed: 16.66 MHz SPI100: Enabled SPI Read Mode: Normal Read (up to 33M) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f37a3b040808d6a5a8e07d39b6d4a1e1981355c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> |
||
|---|---|---|
| 3rdparty | ||
| configs | ||
| Documentation | ||
| LICENSES | ||
| payloads | ||
| spd | ||
| src | ||
| tests | ||
| util | ||
| .checkpatch.conf | ||
| .clang-format | ||
| .editorconfig | ||
| .gitignore | ||
| .gitmodules | ||
| .gitreview | ||
| AUTHORS | ||
| COPYING | ||
| gnat.adc | ||
| MAINTAINERS | ||
| Makefile | ||
| Makefile.inc | ||
| README.md | ||
| toolchain.inc | ||
coreboot README
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
Payloads
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
Supported Hardware
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
Build Requirements
- make
- gcc / g++
Because Linux distribution compilers tend to use lots of patches. coreboot
does lots of "unusual" things in its build system, some of which break due
to those patches, sometimes by gcc aborting, sometimes - and that's worse -
by generating broken object code.
Two options: use our toolchain (eg. make crosstools-i386) or enable the
ANY_TOOLCHAINKconfig option if you're feeling lucky (no support in this case). - iasl (for targets with ACPI support)
- pkg-config
- libssl-dev (openssl)
Optional:
- doxygen (for generating/viewing documentation)
- gdb (for better debugging facilities on some targets)
- ncurses (for
make menuconfigandmake nconfig) - flex and bison (for regenerating parsers)
Building coreboot
Please consult https://www.coreboot.org/Build_HOWTO for details.
Testing coreboot Without Modifying Your Hardware
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Website and Mailing List
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
Copyright and License
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.