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coreboot-kgpe-d16/src/northbridge/intel/x4x
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Stefan Tauner 3e3bae03cf nb/intel/x4x/gma.c: fix skipping of native graphics init 
CB:27984 (e6c8f7e) is supposed to skip over NGI if bit #1 in
register GCC is set. However the check for x4x was wrongly
checking if any bit of the whole register is set.

Change-Id: I5000f5e771abb98f046e2ad19c1bee7dbc0743fc
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-05 13:08:21 +00:00
..
acpi sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables 2018-06-29 07:45:30 +00:00
acpi.c nb/x4x: Get rid of device_t 2018-04-30 09:22:32 +00:00
bootblock.c
chip.h
dq_dqs.c nb/intel/x4x: Implement write leveling 2018-05-24 13:03:45 +00:00
early_init.c nb/intel/x4x: Change memory layout to improve MTRR 2018-05-01 17:42:30 +00:00
gma.c nb/intel/x4x/gma.c: fix skipping of native graphics init 2018-09-05 13:08:21 +00:00
iomap.h
Kconfig nb/intel/x4x: Deprecate native graphic init 2018-06-14 09:40:55 +00:00
Makefile.inc nb/intel/x4x: Switch to POSTCAR_STAGE 2018-06-05 07:49:20 +00:00
northbridge.c nb/intel/x4x: Don't use PCI operations on the pci_domain device 2018-08-01 12:12:22 +00:00
ram_calc.c src/northbridge: Fix typo 2018-08-09 15:51:10 +00:00
raminit.c nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset 2018-06-17 14:17:31 +00:00
raminit_ddr23.c x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2] 2018-08-04 18:44:11 +00:00
raminit_tables.c src: Fix typo 2018-08-10 21:25:53 +00:00
rcven.c nb/intel/x4x/rcven.c: Change the verbosity of some messages 2018-04-17 10:41:57 +00:00
x4x.h northbridge/x4x: add MCHBAR AND/OR/AND_OR access macros 2018-07-30 19:10:02 +00:00