467f31de92
This makes use of the new functions from pmutil.c that take care of the differences between -H and -LP chipsets. It also adds support for the LynxPoint-LP GPE0 register block and the SMI/SCI routing differences. The FADT is updated to report the new 256 byte GPE0 block on wtm2/wtm2 boards which is too big for the 64bit X_GPE0 address block so that part is zeroed to prevent IASL and the kernel from complaining about a mismatch. This was tested on WTM2. Unfortunately I am still unable to get an SCI delivered from the EC but I suspect that is due to a magic command needed to put the EC in ACPI mode. Instead I verified that all of the power management and GPIO registers were set to expected values. I also tested transitions into S3 and S5 from both the kernel and by pressing the power button at the developer mode screen and they all function as expected. Change-Id: Ice9e798ea5144db228349ce90540745c0780b20a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2816 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
84 lines
2.7 KiB
Text
84 lines
2.7 KiB
Text
chip northbridge/intel/haswell
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# Enable DisplayPort 1 Hotplug with 6ms pulse
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register "gpu_dp_d_hotplug" = "0x06"
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# Enable DisplayPort 0 Hotplug with 6ms pulse
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register "gpu_dp_c_hotplug" = "0x06"
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# Enable DVI Hotplug with 6ms pulse
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register "gpu_dp_b_hotplug" = "0x06"
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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end
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chip cpu/intel/haswell
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# Magic APIC ID to locate this chip
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device lapic 0xACAC off end
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register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3)
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register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6)
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register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
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register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3)
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register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6)
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register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
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end
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end
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device domain 0 on
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device pci 00.0 on end # host bridge
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device pci 02.0 on end # vga controller
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chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
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register "pirqa_routing" = "0x8b"
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register "pirqb_routing" = "0x8a"
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register "pirqc_routing" = "0x8b"
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register "pirqd_routing" = "0x8b"
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register "pirqe_routing" = "0x80"
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register "pirqf_routing" = "0x80"
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register "pirqg_routing" = "0x80"
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register "pirqh_routing" = "0x80"
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register "alt_gp_smi_en" = "0x0000"
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register "gpe0_en_1" = "0x00000400"
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register "gpe0_en_2" = "0x00000000"
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register "gpe0_en_3" = "0x00000000"
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register "gpe0_en_4" = "0x00000000"
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register "ide_legacy_combined" = "0x0"
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register "sata_ahci" = "0x1"
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register "sata_port_map" = "0x2"
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device pci 13.0 on end # Smart Sound Audio DSP
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device pci 14.0 on end # USB3 XHCI
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device pci 15.0 off end # Serial I/O DMA
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device pci 15.1 off end # I2C0
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device pci 15.2 off end # I2C1
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device pci 15.3 off end # GSPI0
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device pci 15.4 off end # GSPI1
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device pci 15.5 off end # UART0
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device pci 15.6 off end # UART1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 17.0 off end # SDIO
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device pci 19.0 on end # GbE
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 on end # PCIe Port #2
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device pci 1c.2 on end # PCIe Port #3
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device pci 1c.3 on end # PCIe Port #4
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device pci 1c.4 on end # PCIe Port #5
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device pci 1c.5 on end # PCIe Port #6
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device pci 1d.0 on end # USB2 EHCI
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on end # LPC bridge
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device pci 1f.2 on end # SATA Controller
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device pci 1f.3 on end # SMBus
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device pci 1f.6 on end # Thermal
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end
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end
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end
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