226065834b
Select LPSS UART Base address based on LPSS UART port index. Change-Id: I31b239e7e6b7e9ac8ea2fcfbcbd8cb148ef9e586 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
84 lines
2.3 KiB
C
84 lines
2.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define __SIMPLE_DEVICE__
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#include <assert.h>
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#include <console/uart.h>
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#include <device/pci_def.h>
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#include <intelblocks/gpio.h>
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#include <intelblocks/lpss.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/uart.h>
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#include <soc/pch.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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#include <soc/iomap.h>
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/* Serial IO UART controller legacy mode */
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#define PCR_SERIAL_IO_GPPRVRW7 0x618
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#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))
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static const struct port {
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struct pad_config pads[2]; /* just TX and RX */
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device_t dev;
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} uart_ports[] = {
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{.dev = PCH_DEV_UART0,
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.pads = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* RX */
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PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1)} /* TX */
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},
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{.dev = PCH_DEV_UART1,
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.pads = { PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* RX */
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PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1)} /* TX */
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},
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{.dev = PCH_DEV_UART2,
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.pads = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* RX */
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PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1)} /* TX */
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}
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};
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void pch_uart_init(void)
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{
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uintptr_t base;
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const struct port *p;
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assert(CONFIG_UART_FOR_CONSOLE < ARRAY_SIZE(uart_ports));
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p = &uart_ports[CONFIG_UART_FOR_CONSOLE];
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base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
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uart_common_init(p->dev, base);
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/* Put UART2 in byte access mode for 16550 compatibility */
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if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {
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pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
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PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
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/*
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* Dummy read after setting any of GPPRVRW7.
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* Required for UART 16550 8-bit Legacy mode to become active
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*/
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lpss_clk_read(base);
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}
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gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads));
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}
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#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)
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uintptr_t uart_platform_base(int idx)
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{
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/* We can only have one serial console at a time */
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return UART_BASE_0_ADDR(idx);
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}
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#endif
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