coreboot-kgpe-d16/src/cpu
Edward O'Callaghan 4202f5d3b3 misc,ASL: Trivial - drop trailing blank lines at EOF
Change-Id: I5060052e268c6a6303d77fdf4380a55ac2ad5ae2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6296
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17 02:18:01 +02:00
..
allwinner src: Make use of 'CEIL_DIV(a, b)' macro across tree 2014-07-11 08:39:07 +02:00
amd misc,ASL: Trivial - drop trailing blank lines at EOF 2014-07-17 02:18:01 +02:00
armltd Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
dmp Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
intel intel/haswell: add vmx support w/Kconfig option 2014-07-10 16:46:41 +02:00
qemu-x86 Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
samsung src: Make use of 'CEIL_DIV(a, b)' macro across tree 2014-07-11 08:39:07 +02:00
ti Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
via Drop redundant select CACHE_AS_RAM 2014-07-05 11:33:23 +02:00
x86 src: Make use of 'CEIL_DIV(a, b)' macro across tree 2014-07-11 08:39:07 +02:00
Kconfig Move ARCH_* from board/Kconfig to cpu or soc Kconfig. 2014-05-03 00:25:20 +02:00
Makefile.inc Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00