a4cad368a2
Add PLL and clock init code. TEST=Boots correctly on MT8192EVB. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: Ia49342c058577e8e107b7e56c867bf21532e40d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
82 lines
1.8 KiB
C
82 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mmio.h>
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#include <assert.h>
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#include <soc/pll.h>
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#include <types.h>
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#define GENMASK(h, l) (BIT(h + 1) - BIT(l))
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void mux_set_sel(const struct mux *mux, u32 sel)
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{
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u32 mask = GENMASK(mux->mux_width - 1, 0);
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u32 val = read32(mux->reg);
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if (mux->set_reg && mux->clr_reg) {
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write32(mux->clr_reg, mask << mux->mux_shift);
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write32(mux->set_reg, sel << mux->mux_shift);
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} else {
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val &= ~(mask << mux->mux_shift);
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val |= (sel & mask) << mux->mux_shift;
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write32(mux->reg, val);
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}
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if (mux->upd_reg)
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write32(mux->upd_reg, 1 << mux->upd_shift);
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}
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static void pll_calc_values(const struct pll *pll, u32 *pcw, u32 *postdiv,
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u32 freq)
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{
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const u32 fin_hz = CLK26M_HZ;
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const u32 *div_rate = pll->div_rate;
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u32 val;
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assert(freq <= div_rate[0]);
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assert(freq >= 1 * GHz / 16);
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for (val = 1; div_rate[val] != 0; val++) {
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if (freq > div_rate[val])
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break;
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}
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val--;
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*postdiv = val;
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/* _pcw = freq * 2^postdiv / fin * 2^pcwbits_fractional */
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val += pll->pcwbits - PCW_INTEGER_BITS;
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*pcw = ((u64)freq << val) / fin_hz;
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}
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static void pll_set_rate_regs(const struct pll *pll, u32 pcw, u32 postdiv)
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{
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u32 val;
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/* set postdiv */
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val = read32(pll->div_reg);
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val &= ~(PLL_POSTDIV_MASK << pll->div_shift);
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val |= postdiv << pll->div_shift;
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/* set postdiv and pcw at the same time if on the same register */
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if (pll->div_reg != pll->pcw_reg) {
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write32(pll->div_reg, val);
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val = read32(pll->pcw_reg);
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}
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/* set pcw */
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val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);
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val |= pcw << pll->pcw_shift;
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write32(pll->pcw_reg, val);
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pll_set_pcw_change(pll);
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}
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int pll_set_rate(const struct pll *pll, u32 rate)
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{
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u32 pcw, postdiv;
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pll_calc_values(pll, &pcw, &postdiv, rate);
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pll_set_rate_regs(pll, pcw, postdiv);
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return 0;
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}
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