314c4c3ed6
USBPHY_COMPBG needs to be configured by project
BUG=chrome-os-partner:30690
BRANCH=none
TEST=emerge-rambi coreboot without problem
checked the USBPHY_COMPBG is configured properly
Original-Change-Id: I05eee384d94cf5deeec14418bd78816df0b26a92
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208557
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 20a9c0ab7ab180596821751110f0c0a35d3ff3a1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8bed3fa4e74e4bb4c93fa522d9df631bac2d9795
Reviewed-on: http://review.coreboot.org/8216
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
94 lines
2.8 KiB
C
94 lines
2.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* The devicetree parser expects chip.h to reside directly in the path
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* specified by the devicetree. */
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#ifndef _BAYTRAIL_CHIP_H_
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#define _BAYTRAIL_CHIP_H_
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#include <stdint.h>
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struct soc_intel_baytrail_config {
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uint8_t enable_xdp_tap;
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uint8_t sata_port_map;
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uint8_t sata_ahci;
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uint8_t ide_legacy_combined;
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uint8_t clkreq_enable;
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/* VR low power settings -- enable PS2 mode for gfx and core */
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int vnn_ps2_enable;
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int vcc_ps2_enable;
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/* Disable SLP_X stretching after SUS power well loss. */
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int disable_slp_x_stretch_sus_fail;
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/* USB Port Disable mask */
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uint16_t usb2_port_disable_mask;
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uint16_t usb3_port_disable_mask;
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/* USB routing */
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int usb_route_to_xhci;
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/* USB PHY settings specific to the board */
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uint32_t usb2_per_port_lane0;
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uint32_t usb2_per_port_rcomp_hs_pullup0;
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uint32_t usb2_per_port_lane1;
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uint32_t usb2_per_port_rcomp_hs_pullup1;
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uint32_t usb2_per_port_lane2;
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uint32_t usb2_per_port_rcomp_hs_pullup2;
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uint32_t usb2_per_port_lane3;
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uint32_t usb2_per_port_rcomp_hs_pullup3;
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uint32_t usb2_comp_bg;
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/* LPE Audio Clock configuration. */
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int lpe_codec_clk_freq; /* 19 or 25 are valid. */
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int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */
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/* Native SD Card controller - override controller capabilities. */
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uint32_t sdcard_cap_low;
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uint32_t sdcard_cap_high;
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/* Enable devices in ACPI mode */
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int lpss_acpi_mode;
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int scc_acpi_mode;
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int lpe_acpi_mode;
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/* Allow PCIe devices to wake system from suspend. */
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int pcie_wake_enable;
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int gpu_pipea_port_select; /* Port select: 1=DP_B 2=DP_C */
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uint16_t gpu_pipea_power_on_delay;
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uint16_t gpu_pipea_light_on_delay;
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uint16_t gpu_pipea_power_off_delay;
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uint16_t gpu_pipea_light_off_delay;
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uint16_t gpu_pipea_power_cycle_delay;
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int gpu_pipea_pwm_freq_hz;
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int gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */
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uint16_t gpu_pipeb_power_on_delay;
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uint16_t gpu_pipeb_light_on_delay;
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uint16_t gpu_pipeb_power_off_delay;
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uint16_t gpu_pipeb_light_off_delay;
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uint16_t gpu_pipeb_power_cycle_delay;
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int gpu_pipeb_pwm_freq_hz;
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};
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extern struct chip_operations soc_intel_baytrail_ops;
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#endif /* _BAYTRAIL_CHIP_H_ */
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