6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
92 lines
3.4 KiB
C
92 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <chip.h>
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#include <amdblocks/agesawrapper.h>
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#include <boardid.h>
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#include <gpio.h>
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#include <console/console.h>
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#include <soc/pci_devs.h>
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#define DIMMS_PER_CHANNEL 1
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#if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH
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#error "Too many DIMM sockets defined for the mainboard"
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#endif
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static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
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DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
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NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL),
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NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH),
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MOTHER_BOARD_LAYERS(LAYERS_6),
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MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL,
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0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
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CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
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ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
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CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL,
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0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
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PSO_END
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};
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/* Liara-specific 2T memory configuration */
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static const PSO_ENTRY DDR4_2T_MemoryConfiguration[] = {
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DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
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NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL),
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NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH),
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MOTHER_BOARD_LAYERS(LAYERS_6),
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MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL,
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0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
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CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
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ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
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CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL,
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0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
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TBLDRV_CONFIG_TO_OVERRIDE(DIMMS_PER_CHANNEL, ANY_SPEED, VOLT_ANY_,
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ANY_),
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TBLDRV_CONFIG_ENTRY_SLOWACCMODE(1),
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PSO_END
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};
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void OemPostParams(AMD_POST_PARAMS *PostParams)
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{
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if (CONFIG(BOARD_GOOGLE_LIARA) || CONFIG(BOARD_GOOGLE_TREEYA))
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PostParams->MemConfig.PlatformMemoryConfiguration =
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(PSO_ENTRY *)DDR4_2T_MemoryConfiguration;
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else
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PostParams->MemConfig.PlatformMemoryConfiguration =
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(PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
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/*
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* Bank interleaving is enabled by default in AGESA. However, from AMD's
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* explanation, bank interleaving is really chip select interleave,
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* requiring 2 chip select arriving to the DIMM (rank interleaving). As
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* both kahlee and grunt are hardware limited to a single chip select
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* arriving at the DIMM, interleave will not work. This causes AGESA to
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* throw a warning. To avoid the warning, interleaving needs to be
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* disabled.
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*/
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PostParams->MemConfig.EnableBankIntlv = FALSE;
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}
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void set_board_env_params(GNB_ENV_CONFIGURATION *params)
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{
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const struct soc_amd_stoneyridge_config *cfg;
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const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
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if (!dev || !dev->chip_info) {
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printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree config\n");
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return;
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}
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cfg = dev->chip_info;
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if (cfg->lvds_poseq_blon_to_varybl && cfg->lvds_poseq_varybl_to_blon) {
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/*
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* GPIO 133 - Backlight enable (active low)
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* Pass control of the backlight to the video BIOS
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*/
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gpio_set(GPIO_133, 0);
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printk(BIOS_INFO, "Change panel init timing\n");
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params->LvdsPowerOnSeqVaryBlToBlon =
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cfg->lvds_poseq_varybl_to_blon;
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params->LvdsPowerOnSeqBlonToVaryBl =
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cfg->lvds_poseq_blon_to_varybl;
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printk(BIOS_INFO, "LvdsPowerOnSeqVaryBlToBlon: %dms\n",
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(params->LvdsPowerOnSeqVaryBlToBlon)*4);
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printk(BIOS_INFO, "LvdsPowerOnSeqBlonToVaryBl: %dms\n",
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(params->LvdsPowerOnSeqBlonToVaryBl)*4);
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}
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params->EDPv1_4VSMode = EDP_VS_HIGH_VDIFF_MODE;
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}
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