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coreboot-kgpe-d16/src/mainboard/google/kahlee/OemCustomize.c

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mb/google/kahlee: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I78f386eb47fc9b91992884e309dbbf33fb3d4e92 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40179 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-05 13:21:48 +02:00
/* SPDX-License-Identifier: GPL-2.0-only */
google/kahlee: Start Kahlee mainboard Copied from amd/gardenia. Update the appropriate board name strings. Uses the soc/ structure. Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-23 05:35:16 +02:00
google/kahlee: Add defines in OemCustomize.c Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max supported for the device. AGESA's DRAM procedures follow the BKDG and may vary depending on the number of slots on the motherboard. DIMM numbering and ordering is also affected by this value. Replace hardcoded integers with defined values for DIMM slots and number of channels. Change-Id: I4f7336da80b4e3d7f351502a63de0652e9ff5395 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21853 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-25 18:11:50 +02:00
#include <chip.h>
soc/amd/common: Move Agesa related headers Move AGESA related headers in soc/amd/common to soc/amd/common/block/include/amdblocks. BUG=b:69262110 TEST=Build with no error gardenia and kahlee (no code change, headers moved). Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-09 00:53:29 +01:00
#include <amdblocks/agesawrapper.h>
mb/google/kahlee: Enable 2T mode for liara Liara auto restart issue is caused by memory access error and consequent kernel panic. To solve this issue, revert the CL:1243666 (Disable NbP-state on Liara) and use 2T mode instead. BUG=b:116082728 TEST=verify the 2T mode is enabled/boot into ChromeOS and no auto restart/run memtester passed 10 cycle. Change-Id: I3a96276d88ffb70530d72b15c07b59a01cc6209a Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-18 12:52:58 +02:00
#include <boardid.h>
mb/google/kahlee: Tune eDP panel initialization time 1. Add two parameters for panel initialization timing. > lvds_poseq_varybl_to_blon > lvds_poseq_blon_to_varybl 2. The BL_PWM is controlled by APU_EDP_BKLTEN_L/APU_DP_VARY_BL/ EDP_BKLTEN_L, so move APU_EDP_BKLTEN_L to early init stage, and be enabled depends on SKU, thus we can control the delay time by config APU_DP_VARY_BL. BUG=b:118011567 TEST=emerge-grunt coreboot. Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-05 05:09:24 +01:00
#include <gpio.h>
#include <console/console.h>
#include <soc/pci_devs.h>
google/kahlee: Start Kahlee mainboard Copied from amd/gardenia. Update the appropriate board name strings. Uses the soc/ structure. Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-23 05:35:16 +02:00
google/kahlee: Add defines in OemCustomize.c Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max supported for the device. AGESA's DRAM procedures follow the BKDG and may vary depending on the number of slots on the motherboard. DIMM numbering and ordering is also affected by this value. Replace hardcoded integers with defined values for DIMM slots and number of channels. Change-Id: I4f7336da80b4e3d7f351502a63de0652e9ff5395 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21853 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-25 18:11:50 +02:00
#define DIMMS_PER_CHANNEL 1
#if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH
#error "Too many DIMM sockets defined for the mainboard"
#endif
google/kahlee: Start Kahlee mainboard Copied from amd/gardenia. Update the appropriate board name strings. Uses the soc/ structure. Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-23 05:35:16 +02:00
static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
google/kahlee: Add defines in OemCustomize.c Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max supported for the device. AGESA's DRAM procedures follow the BKDG and may vary depending on the number of slots on the motherboard. DIMM numbering and ordering is also affected by this value. Replace hardcoded integers with defined values for DIMM slots and number of channels. Change-Id: I4f7336da80b4e3d7f351502a63de0652e9ff5395 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21853 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-25 18:11:50 +02:00
NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL),
NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH),
google/kahlee: Start Kahlee mainboard Copied from amd/gardenia. Update the appropriate board name strings. Uses the soc/ structure. Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-23 05:35:16 +02:00
MOTHER_BOARD_LAYERS(LAYERS_6),
MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL,
0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL,
0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
PSO_END
};
mb/google/kahlee: Remove board_id check for Liara 2T timings Use 2T memory timings on Liara for all board IDs. BUG=b:116082728 TEST=Build & boot on Liara Change-Id: I5814e63db35cf7761f4f20792b0f3cf4120a1b60 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/30285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-12-17 21:33:10 +01:00
/* Liara-specific 2T memory configuration */
mb/google/kahlee/treeya: Update the memory timing table for Treeya to the 2T table Rename the table from Liara specific to simply specifying that it's using 2T command rate BUG=139841929 TEST=build and do stress test Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6e10b95c8aea50e68d8a3b710f30dda4f6b807d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-27 10:51:04 +02:00
static const PSO_ENTRY DDR4_2T_MemoryConfiguration[] = {
mb/google/kahlee: Enable 2T mode for liara Liara auto restart issue is caused by memory access error and consequent kernel panic. To solve this issue, revert the CL:1243666 (Disable NbP-state on Liara) and use 2T mode instead. BUG=b:116082728 TEST=verify the 2T mode is enabled/boot into ChromeOS and no auto restart/run memtester passed 10 cycle. Change-Id: I3a96276d88ffb70530d72b15c07b59a01cc6209a Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-18 12:52:58 +02:00
DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL),
NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH),
MOTHER_BOARD_LAYERS(LAYERS_6),
MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL,
0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL,
0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
TBLDRV_CONFIG_TO_OVERRIDE(DIMMS_PER_CHANNEL, ANY_SPEED, VOLT_ANY_,
ANY_),
TBLDRV_CONFIG_ENTRY_SLOWACCMODE(1),
PSO_END
};
google/kahlee: Start Kahlee mainboard Copied from amd/gardenia. Update the appropriate board name strings. Uses the soc/ structure. Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-23 05:35:16 +02:00
void OemPostParams(AMD_POST_PARAMS *PostParams)
{
mb/google/kahlee/treeya: Update the memory timing table for Treeya to the 2T table Rename the table from Liara specific to simply specifying that it's using 2T command rate BUG=139841929 TEST=build and do stress test Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6e10b95c8aea50e68d8a3b710f30dda4f6b807d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-27 10:51:04 +02:00
if (CONFIG(BOARD_GOOGLE_LIARA) || CONFIG(BOARD_GOOGLE_TREEYA))
mb/google/kahlee: Enable 2T mode for liara Liara auto restart issue is caused by memory access error and consequent kernel panic. To solve this issue, revert the CL:1243666 (Disable NbP-state on Liara) and use 2T mode instead. BUG=b:116082728 TEST=verify the 2T mode is enabled/boot into ChromeOS and no auto restart/run memtester passed 10 cycle. Change-Id: I3a96276d88ffb70530d72b15c07b59a01cc6209a Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-18 12:52:58 +02:00
PostParams->MemConfig.PlatformMemoryConfiguration =
mb/google/kahlee/treeya: Update the memory timing table for Treeya to the 2T table Rename the table from Liara specific to simply specifying that it's using 2T command rate BUG=139841929 TEST=build and do stress test Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6e10b95c8aea50e68d8a3b710f30dda4f6b807d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-27 10:51:04 +02:00
(PSO_ENTRY *)DDR4_2T_MemoryConfiguration;
mb/google/kahlee: Enable 2T mode for liara Liara auto restart issue is caused by memory access error and consequent kernel panic. To solve this issue, revert the CL:1243666 (Disable NbP-state on Liara) and use 2T mode instead. BUG=b:116082728 TEST=verify the 2T mode is enabled/boot into ChromeOS and no auto restart/run memtester passed 10 cycle. Change-Id: I3a96276d88ffb70530d72b15c07b59a01cc6209a Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-18 12:52:58 +02:00
else
PostParams->MemConfig.PlatformMemoryConfiguration =
(PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
mb/google/kahlee/OemCustomize.c: Disable bank interleave AmdInitPost returns AGESA_WARNING. This is because AGESA by default enables bank interleaving, while the HW does not meet the requirements for it. Disable bank interleaving, thus clearing AGESA_WARNING. BUG=b:73118857 TEST= Build and run kahlee. Search for "agesawrapper_amdinitpost() returned AGESA_SUCCESS". Change-Id: Ice9270f9b10051dbb622344919223cf5439f5d7b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-16 22:33:59 +01:00
/*
* Bank interleaving is enabled by default in AGESA. However, from AMD's
* explanation, bank interleaving is really chip select interleave,
* requiring 2 chip select arriving to the DIMM (rank interleaving). As
* both kahlee and grunt are hardware limited to a single chip select
* arriving at the DIMM, interleave will not work. This causes AGESA to
* throw a warning. To avoid the warning, interleaving needs to be
* disabled.
*/
PostParams->MemConfig.EnableBankIntlv = FALSE;
google/kahlee: Start Kahlee mainboard Copied from amd/gardenia. Update the appropriate board name strings. Uses the soc/ structure. Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-23 05:35:16 +02:00
}
mb/google/kahlee/OemCustomize.c: Enable eDP HIGH_VDIFF The careena board needs different video settings to pass eye diagram test, which does not affect negatively the grunt board. In preparation for new VBIOS, AGESA environment needs eDP high vdiff enabled. BUG=b:111673328 TEST=Add debug code to AGESA to display set eDP. Build AGESA. Build and boot grunt. Add new code to grunt, build and boot, verify eDP changed. Change-Id: I3e6b409699e8192eb39cc189628ff95b9f985e54 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-27 21:44:22 +02:00
void set_board_env_params(GNB_ENV_CONFIGURATION *params)
{
mb/google/kahlee: Tune eDP panel initialization time 1. Add two parameters for panel initialization timing. > lvds_poseq_varybl_to_blon > lvds_poseq_blon_to_varybl 2. The BL_PWM is controlled by APU_EDP_BKLTEN_L/APU_DP_VARY_BL/ EDP_BKLTEN_L, so move APU_EDP_BKLTEN_L to early init stage, and be enabled depends on SKU, thus we can control the delay time by config APU_DP_VARY_BL. BUG=b:118011567 TEST=emerge-grunt coreboot. Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-05 05:09:24 +01:00
const struct soc_amd_stoneyridge_config *cfg;
device: Use pcidev_path_on_root() Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-06-21 15:20:55 +02:00
const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
mb/google/kahlee: Tune eDP panel initialization time 1. Add two parameters for panel initialization timing. > lvds_poseq_varybl_to_blon > lvds_poseq_blon_to_varybl 2. The BL_PWM is controlled by APU_EDP_BKLTEN_L/APU_DP_VARY_BL/ EDP_BKLTEN_L, so move APU_EDP_BKLTEN_L to early init stage, and be enabled depends on SKU, thus we can control the delay time by config APU_DP_VARY_BL. BUG=b:118011567 TEST=emerge-grunt coreboot. Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-11-05 05:09:24 +01:00
if (!dev || !dev->chip_info) {
printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree config\n");
return;
}
cfg = dev->chip_info;
if (cfg->lvds_poseq_blon_to_varybl && cfg->lvds_poseq_varybl_to_blon) {
/*
* GPIO 133 - Backlight enable (active low)
* Pass control of the backlight to the video BIOS
*/
gpio_set(GPIO_133, 0);
printk(BIOS_INFO, "Change panel init timing\n");
params->LvdsPowerOnSeqVaryBlToBlon =
cfg->lvds_poseq_varybl_to_blon;
params->LvdsPowerOnSeqBlonToVaryBl =
cfg->lvds_poseq_blon_to_varybl;
printk(BIOS_INFO, "LvdsPowerOnSeqVaryBlToBlon: %dms\n",
(params->LvdsPowerOnSeqVaryBlToBlon)*4);
printk(BIOS_INFO, "LvdsPowerOnSeqBlonToVaryBl: %dms\n",
(params->LvdsPowerOnSeqBlonToVaryBl)*4);
}
mb/google/kahlee/OemCustomize.c: Enable eDP HIGH_VDIFF The careena board needs different video settings to pass eye diagram test, which does not affect negatively the grunt board. In preparation for new VBIOS, AGESA environment needs eDP high vdiff enabled. BUG=b:111673328 TEST=Add debug code to AGESA to display set eDP. Build AGESA. Build and boot grunt. Add new code to grunt, build and boot, verify eDP changed. Change-Id: I3e6b409699e8192eb39cc189628ff95b9f985e54 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-27 21:44:22 +02:00
params->EDPv1_4VSMode = EDP_VS_HIGH_VDIFF_MODE;
}
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