8a41f4b71e
These are defined for __SIMPLE_DEVICE__ when PCI enumeration has not happened yet. These should not really try to probe devices other than those on bus 0. It's hard to track but there maybe cases of southbridge being located on bus 2 and available for configuration, so I rather leave the code unchanged. Just move these out of arch/io.h because they cause build failures if one attempts to include <arch/pci_ops.h> before <arch/io.h>. There are two direct copies for ROMCC bootblocks to avoid inlining them elsewhere. Change-Id: Ida2919a5d83fe5ea89284ffbd8ead382e4312524 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
46 lines
1.3 KiB
C
46 lines
1.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <arch/io.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include "i82371eb.h"
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void enable_pm(void)
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{
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pci_devfn_t dev;
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u8 reg8;
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u16 reg16;
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/* Get the SMBus/PM device of the 82371AB/EB/MB. */
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dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
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/* Set the PM I/O base. */
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pci_write_config32(dev, PMBA, DEFAULT_PMBASE | 1);
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/* Enable access to the PM I/O space. */
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 |= PCI_COMMAND_IO;
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pci_write_config16(dev, PCI_COMMAND, reg16);
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/* PM I/O Space Enable (PMIOSE). */
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reg8 = pci_read_config8(dev, PMREGMISC);
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reg8 |= PMIOSE;
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pci_write_config8(dev, PMREGMISC, reg8);
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}
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