device/pci_ops: Move questionable pci_locate() variants

These are defined for __SIMPLE_DEVICE__ when PCI
enumeration has not happened yet. These should not
really try to probe devices other than those on bus 0.

It's hard to track but there maybe cases of southbridge
being located on bus 2 and available for configuration, so
I rather leave the code unchanged. Just move these out of
arch/io.h because they cause build failures if one attempts
to include <arch/pci_ops.h> before <arch/io.h>.

There are two direct copies for ROMCC bootblocks to
avoid inlining them elsewhere.

Change-Id: Ida2919a5d83fe5ea89284ffbd8ead382e4312524
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/arch/x86/include/arch/io.h

@@ -205,10 +205,6 @@ static __always_inline void write64(volatile void *addr,
 
 #ifdef __SIMPLE_DEVICE__
 
-#define PCI_ID(VENDOR_ID, DEVICE_ID) \
-	((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
-
-
 #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
 
 #include <arch/pci_io_cfg.h>
@@ -268,47 +264,6 @@ void pci_write_config32(pci_devfn_t dev, unsigned int where, uint32_t value)
 		pci_io_write_config32(dev, where, value);
 }
 
-static inline pci_devfn_t pci_io_locate_device(unsigned int pci_id,
-	pci_devfn_t dev)
-{
-	for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
-		unsigned int id;
-		id = pci_io_read_config32(dev, 0);
-		if (id == pci_id)
-			return dev;
-	}
-	return PCI_DEV_INVALID;
-}
-
-static inline pci_devfn_t pci_locate_device(unsigned int pci_id,
-	pci_devfn_t dev)
-{
-	for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
-		unsigned int id;
-		id = pci_read_config32(dev, 0);
-		if (id == pci_id)
-			return dev;
-	}
-	return PCI_DEV_INVALID;
-}
-
-static inline pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id,
-	unsigned int bus)
-{
-	pci_devfn_t dev, last;
-
-	dev = PCI_DEV(bus, 0, 0);
-	last = PCI_DEV(bus, 31, 7);
-
-	for (; dev <= last; dev += PCI_DEV(0, 0, 1)) {
-		unsigned int id;
-		id = pci_read_config32(dev, 0);
-		if (id == pci_id)
-			return dev;
-	}
-	return PCI_DEV_INVALID;
-}
-
 /* Generic functions for pnp devices */
 static __always_inline void pnp_write_config(
 	pnp_devfn_t dev, uint8_t reg, uint8_t value)

src/device/pci_early.c

@@ -165,3 +165,34 @@ void pci_early_bridge_init(void)
 
 	pci_early_mmio_window(p2p_bridge, CONFIG_EARLY_PCI_MMIO_BASE, 0x4000);
 }
+
+/* FIXME: A lot of issues using the following, please avoid.
+ * Assumes 256 PCI busses, scans them all even when PCI bridges are still
+ * disabled. Probes all functions even if 0 is not present.
+ */
+pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev)
+{
+	for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
+		unsigned int id;
+		id = pci_read_config32(dev, 0);
+		if (id == pci_id)
+			return dev;
+	}
+	return PCI_DEV_INVALID;
+}
+
+pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus)
+{
+	pci_devfn_t dev, last;
+
+	dev = PCI_DEV(bus, 0, 0);
+	last = PCI_DEV(bus, 31, 7);
+
+	for (; dev <= last; dev += PCI_DEV(0, 0, 1)) {
+		unsigned int id;
+		id = pci_read_config32(dev, 0);
+		if (id == pci_id)
+			return dev;
+	}
+	return PCI_DEV_INVALID;
+}

src/include/device/pci.h

@@ -133,6 +133,12 @@ static inline const struct pci_operations *ops_pci(struct device *dev)
 	return pops;
 }
 
+#define PCI_ID(VENDOR_ID, DEVICE_ID) \
+	((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
+
+pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev);
+pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus);
+
 #ifdef __SIMPLE_DEVICE__
 unsigned int pci_find_next_capability(pci_devfn_t dev, unsigned int cap,
 	unsigned int last);

src/southbridge/amd/amd8111/bootblock.c

@@ -17,6 +17,21 @@
 #include <stdint.h>
 #include <arch/io.h>
 #include <device/pci_ids.h>
+#include <device/pci_type.h>
+
+#define PCI_ID(VENDOR_ID, DEVICE_ID) \
+	((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
+
+static pci_devfn_t pci_io_locate_device(unsigned int pci_id, pci_devfn_t dev)
+{
+	for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
+		unsigned int id;
+		id = pci_io_read_config32(dev, 0);
+		if (id == pci_id)
+			return dev;
+	}
+	return PCI_DEV_INVALID;
+}
 
 /* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */
 static void amd8111_enable_rom(void)

src/southbridge/amd/amd8111/reset.c

@@ -16,6 +16,7 @@
 
 #include <arch/io.h>
 #include <reset.h>
+#include <device/pci.h>
 #include <device/pci_ids.h>
 
 

src/southbridge/amd/sb700/early_setup.c

@@ -22,6 +22,7 @@
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
+#include <device/pci.h>
 
 #include <reset.h>
 #include "sb700.h"

src/southbridge/broadcom/bcm5785/bootblock.c

@@ -17,6 +17,21 @@
 #include <stdint.h>
 #include <arch/io.h>
 #include <device/pci_ids.h>
+#include <device/pci_type.h>
+
+#define PCI_ID(VENDOR_ID, DEVICE_ID) \
+	((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
+
+static pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev)
+{
+	for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
+		unsigned int id;
+		id = pci_read_config32(dev, 0);
+		if (id == pci_id)
+			return dev;
+	}
+	return PCI_DEV_INVALID;
+}
 
 /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
 static void bcm5785_enable_rom(void)

src/southbridge/intel/i82371eb/bootblock.c

@@ -17,8 +17,23 @@
 #include <stdint.h>
 #include <arch/io.h>
 #include <device/pci_ids.h>
+#include <device/pci_type.h>
 #include "i82371eb.h"
 
+#define PCI_ID(VENDOR_ID, DEVICE_ID) \
+	((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
+
+static pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev)
+{
+	for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
+		unsigned int id;
+		id = pci_read_config32(dev, 0);
+		if (id == pci_id)
+			return dev;
+	}
+	return PCI_DEV_INVALID;
+}
+
 static void bootblock_southbridge_init(void)
 {
 	u16 reg16;

src/southbridge/intel/i82371eb/early_pm.c

@@ -16,6 +16,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include "i82371eb.h"

src/southbridge/intel/i82371eb/early_smbus.c

@@ -16,6 +16,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
 #include <southbridge/intel/common/smbus.h>

src/southbridge/nvidia/ck804/early_smbus.c

@@ -17,6 +17,7 @@
 #include <stdint.h>
 #include <arch/io.h>
 #include <console/console.h>
+#include <device/pci.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 

src/southbridge/nvidia/mcp55/early_smbus.c

@@ -19,6 +19,7 @@
 
 #include <arch/io.h>
 #include <console/console.h>
+#include <device/pci.h>
 #include "smbus.h"
 #include "mcp55.h"