Patrick Rudolph 2031221fbd soc/intel/cannonlake: Change mainboard_silicon_init_params argument ... Use FSPS_UPD instead of FSP_S_CONFIG as argument as already done on xeon_sp and denverton_ns. This allows to set test config UPDs from mainboard code as well. Change-Id: I6d67264e22df32b9210ce88b99d6a7a4f6b97ffb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>		2020-12-17 06:22:55 +00:00
..
spd	mb: remove duplicated Make code for spd.bin generation	2020-09-06 14:57:06 +00:00
variants	hatch: enable genesis PCIe/USB devices	2020-12-11 18:04:30 +00:00
board_info.txt
bootblock.c
chromeos-hatch-16MiB.fmd
chromeos-hatch-32MiB.fmd
chromeos-puff-16MiB.fmd
chromeos-puff-32MiB.fmd
chromeos.c
dsdt.asl	soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD	2020-11-20 00:12:09 +00:00
ec.c
Kconfig	src/lib: Add Kconfig option for SPD cache in FMAP	2020-12-14 08:23:41 +00:00
Kconfig.name	hatch: Create genesis variant	2020-11-09 10:18:07 +00:00
Makefile.inc
ramstage.c	soc/intel/cannonlake: Change mainboard_silicon_init_params argument	2020-12-17 06:22:55 +00:00
romstage_spd_cbfs.c	mb/google/hatch,dedede,volteer: enable CHROMEOS_DRAM_PART_NUMBER_IN_CBI	2020-10-05 18:03:38 +00:00
romstage_spd_smbus.c	src: Add missing 'include <console/console.h>'	2020-11-17 09:01:14 +00:00
smihandler.c