coreboot-kgpe-d16/src/soc/intel/braswell/memmap.c
Martin Roth 0639bff5ba src: Update some incorrect config options in comments
This is a trivial patch to fix some comments that were generating
notes in the kconfig lint test.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I26a95f17e82910f50c62215be5c29780fe98e29a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47366
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-16 12:09:58 +00:00

57 lines
1.6 KiB
C

/* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h>
#include <cpu/x86/smm.h>
#include <soc/iosf.h>
static size_t smm_region_size(void)
{
u32 smm_size;
smm_size = iosf_bunit_read(BUNIT_SMRRH) & 0xFFFF;
smm_size -= iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF;
smm_size = (smm_size + 1) << 20;
return smm_size;
}
void smm_region(uintptr_t *start, size_t *size)
{
*start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20;
*size = smm_region_size();
}
void *cbmem_top_chipset(void)
{
uintptr_t smm_base;
size_t smm_size;
/*
* +-------------------------+ Top of RAM (aligned)
* | System Management Mode |
* | code and data | Length: CONFIG_SMM_TSEG_SIZE
* | (TSEG) |
* +-------------------------+ SMM base (aligned)
* | |
* | Chipset Reserved Memory | Length: Multiple of CONFIG_SMM_TSEG_SIZE
* | |
* +-------------------------+ top_of_ram (aligned)
* | |
* | CBMEM Root |
* | |
* +-------------------------+
* | |
* | FSP Reserved Memory |
* | |
* +-------------------------+
* | |
* | Various CBMEM Entries |
* | |
* +-------------------------+ top_of_stack (8 byte aligned)
* | |
* | stack (CBMEM Entry) |
* | |
* +-------------------------+
*/
smm_region(&smm_base, &smm_size);
return (void *)smm_base;
}