Angel Pons 6f5a6581a6 src: Introduce ARCH_ALL_STAGES_X86 ... Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically select the per-stage arch options. Subsequent commits will leverage this to allow choosing between 32-bit and 64-bit coreboot where all stages are x86. AMD Picasso and AMD Cezanne are the only exceptions to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set the per-stage arch options accordingly. Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>		2021-07-02 08:19:10 +00:00
..
acpi	soc/intel/baytrail,braswell: Drop aliases on MMCONF_BASE_ADDRESS	2021-02-16 08:08:01 +00:00
bootblock
include/soc	soc/intel/braswell: Factor out common acpi_fill_madt	2021-03-12 15:41:35 +00:00
romstage
acpi.c	ACPI: Refactor use of global and device NVS	2021-06-14 19:45:56 +00:00
chip.c
chip.h
cpu.c
elog.c	soc/intel: Remove unused <console/console.h>	2021-02-15 10:50:09 +00:00
emmc.c
fadt.c
gfx.c
gpio.c
gpio_support.c
iosf.c
Kconfig	src: Introduce ARCH_ALL_STAGES_X86	2021-07-02 08:19:10 +00:00
lpc_init.c
lpe.c
lpss.c
Makefile.inc	cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y	2021-05-18 16:54:21 +00:00
memmap.c
northcluster.c	nb,soc/intel: Switch to CHROMEOS_RAMOOPS_DYNAMIC	2021-02-16 09:38:29 +00:00
pcie.c
placeholders.c
pmutil.c	soc/intel/braswell/pmutil.c: Define __SIMPLE_DEVICE__	2021-04-19 10:45:06 +00:00
ramstage.c	soc/intel/{baytrail,braswell,broadwell}: Remove unused <string.h>	2021-02-16 17:28:12 +00:00
sata.c	soc/intel: Remove unused <console/console.h>	2021-02-15 10:50:09 +00:00
scc.c	soc/intel: Remove unused <console/console.h>	2021-02-15 10:50:09 +00:00
sd.c
smbus.c	soc/intel/braswell/smbus.c: Define __SIMPLE_DEVICE__	2021-04-19 10:44:40 +00:00
smihandler.c
smm.c
southcluster.c
tsc_freq.c	src: use ARRAY_SIZE where possible	2021-02-15 11:30:40 +00:00
xhci.c