Michael Niewöhner 46ef536212 soc/intel/icelake: correct wrong gpio SMI register base offsets ... Reference: Intel doc# 341081-002. Change-Id: If6e0503cc042c26c4077b8b32bb447d4e3a9bb6a Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>		2021-09-23 06:31:58 +00:00
..
amd	soc/amd/common/block/gpio_banks: Rework GPIO pad configuration	2021-09-22 15:54:52 +00:00
cavium
example	src: Introduce ARCH_ALL_STAGES_X86	2021-07-02 08:19:10 +00:00
intel	soc/intel/icelake: correct wrong gpio SMI register base offsets	2021-09-23 06:31:58 +00:00
mediatek	mipi: Make panel init callback work directly on DSI transaction types	2021-09-11 01:42:47 +00:00
nvidia	mipi: Make panel init callback work directly on DSI transaction types	2021-09-11 01:42:47 +00:00
qualcomm	soc/qualcomm/common: Move UART SC7180 driver to common section	2021-09-23 04:43:59 +00:00
rockchip	mipi: Make panel init callback work directly on DSI transaction types	2021-09-11 01:42:47 +00:00
samsung
sifive
ti
ucb