132 lines
6.1 KiB
Markdown
132 lines
6.1 KiB
Markdown
# Beaglebone Black
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This page gives some details about the [BeagleBone Black] coreboot port and
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describes how to build and run it.
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The port currently only supports booting coreboot from a micro SD card and has
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some other limitations listed below.
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## Supported Boards
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The Beaglebone port supports the following boards:
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- Beaglebone Black
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- Beaglebone Black Wireless
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- Beaglebone Pocket (untested, may need tweaking)
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- Beaglebone Blue (untested, may need tweaking)
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- Beaglebone Original (untested, may need tweaking)
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## Use Cases
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This port was primarily developed as a learning exercise and there is
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potentially little reason to use it compared to the defacto bootloader choice of
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U-Boot. However, it does have some interesting practical use cases compared to
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U-Boot:
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1. Choosing coreboot as a lightweight alternative to U-Boot. In this case,
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coreboot is used to do the absolute minimum necessary to boot Linux, forgoing
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some U-Boot features and functionality. Complex boot logic can then instead
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be moved into Linux where it can be more flexibly and safely executed. This
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is essentially the LinuxBoot philosophy. [U-Boot Falcon mode] has similar
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goals to this as well.
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2. Facilitating experimenting with coreboot on real hardware. The Beaglebone
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Black is widely available at a low pricepoint (~$65) making it a great way to
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experiment with coreboot on real ARMv7 hardware. It also works well as a
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development platform as it has exposed pads for JTAG and, due to the way it
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boots, is effectively impossible to brick.
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3. The Beaglebone Black is often used as a external flasher and EHCI debug
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gadget in the coreboot community, so many members have access to it and can
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use it as a reference platform.
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## Quickstart
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1. Run `make menuconfig` and select _TI_/_Beaglebone_ in the _Mainboard_ menu.
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2. Add a payload as normal.
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3. Run `make`.
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4. Copy the resulting `build/MLO` file to the micro SD card at offset 128k - ie
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`dd if=build/MLO of=/dev/sdcard seek=1 bs=128k`.
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**NOTE**: By default, the Beaglebone is configured to try to boot first from
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eMMC before booting from SD card. To ensure that the Beaglebone boots from SD,
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either erase the internal eMMC or hold the _S2_ button while powering on (note
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that this has to be while powering on - ie when plugging in the USB or DC barrel
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jack - the boot order doesn't change on reset) to prioritize SD in the boot
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order.
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## Serial Console
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By default, coreboot uses UART0 as the serial console. UART0 is available
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through the J1 header on both the Beaglebone Black and Beaglebone Black
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Wireless. The serial runs at 3.3V and 115200 8n1.
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The pin mapping is shown below for J1.
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```eval_rst
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+----------------------------+------------+
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| Pin number | Function |
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+============================+============+
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| 1 (Closest to barrel jack) | GND |
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+----------------------------+------------+
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| 4 | RX |
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+----------------------------+------------+
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| 5 | TX |
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+----------------------------+------------+
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```
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## Boot Process
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The AM335x contains ROM code to allow booting in a number of different
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configurations. More information about the boot ROM code can be found in the
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AM335x technical reference manual (_SPRUH73Q_) in the _Initialization_ section.
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This coreboot port is currently configured to boot in "SD Raw Mode" where the
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boot binary, with header ("Table of Contents" in TI's nomenclature), is placed
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at the offset of 0x20000 (128KB) on the SD card. The boot ROM loads the coreboot
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bootblock stage into SRAM and executes it.
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The bootblock and subsequent romstage and ramstage coreboot stages expect that
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the coreboot image, containing the CBFS, is located at 0x20000 on the SD card.
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All stages directly read from the SD card in order to load the next stage in
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sequence.
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## Clock Initialization and PMIC
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To simplify the port, the TPS65217C Power Management IC (PMIC) on the Beaglebone
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Black is not configured by coreboot. By default, the PMIC reset values for
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VDD_MPU (1.1V) and VDD_CORE (1.8V) are within the Operating Performance Point
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(OPP) for the MPU PLL configuration set by the boot ROM of 500 MHz.
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When using Linux as a payload, the kernel will appropriately scale the core
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voltages for the desired MPU clock frequency as defined in the device tree.
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One significant difference because of this to the U-Boot port is that the DCDC1
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rail that powers the DDR3 RAM will be 1.5V by default. The Micron DDR3 supports
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both 1.35V and 1.5V and U-Boot makes use of this by setting it to 1.35V to
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conserve power. Fortunately, Linux is again able to configure this rail but it
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involves adding an entry to the device tree:
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&dcdc1_reg {
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regulator-name = "vdd_ddr3";
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
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regulator-boot-on;
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regulator-always-on;
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};
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If this port was to be extended to work with boards or SoCs with different
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requirements for the MPU clock frequency or different Operating Performance
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Points, then the port may need to be extended to set the core voltages and MPU
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PLL within coreboot, prior to loading a payload. Extending coreboot so that it
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can configure the PMIC would also be necessary if there was a requirement for
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coreboot to run at a different MPU frequency than the 500 MHz set by the boot
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ROM.
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# Todo
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- Allow coreboot to run from the Beaglebone Black's internal eMMC. This would
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require updating the `mmc.c` driver to support running from both SD and eMMC.
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- Support the boot ROMs *FAT mode* so that the coreboot binary can be placed on
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a FAT partition.
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- Increase the MMC read speed, it currently takes ~15s to read ~20MB which is a
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bit slow. To do this, it should be possible to update the MMC driver to:
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- Increase the supported blocksize (currently is always set to 1)
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- Support 4-bit data width (currently only supports 1-bit data width)
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- Convert the while loops in the MMC driver to timeout so that coreboot does not
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hang on a bad SD card or when the SD card is removed during boot.
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[Beaglebone Black]: https://beagleboard.org/black
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[U-Boot Falcon mode]: https://elixir.bootlin.com/u-boot/v2020.07/source/doc/README.falcon
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