David Hendricks 4bd65e1c0c rk3288: Allow board-specific APLL (CPU clock) settings ... This changes the API to rkclk_configure_cpu() such that we can pass in the desired APLL frequency in each veyron board's bootblock.c. Devices with a constrainted form facter (rialto and possibly mickey) will use this to run firmware at a slower speed to mitigate risk of thermal issues (due to the RK808, not the RK3288). BUG=chrome-os-partner:42054 BRANCH=none TEST=amstan says rialto is noticably cooler (and slower) Change-Id: I28b332e1d484bd009599944cd9f5cf633ea468dd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d10af5e18b4131a00f202272e405bd22eab4caeb Original-Change-Id: I960cb6ff512c058e72032aa2cbadedde97510631 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297190 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11582 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2015-09-08 11:50:50 +00:00
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sdram_inf	veyron: add Nanya NT5CC256M16DP sdram	2015-08-28 06:45:03 +00:00
board.h
boardid.c
bootblock.c	rk3288: Allow board-specific APLL (CPU clock) settings	2015-09-08 11:50:50 +00:00
chromeos.c	veyron_mickey: Apply differences between Brain and Mickey	2015-06-23 08:21:23 +02:00
devicetree.cb	veyron_*: Set vop_mode in devicetree.cb files	2015-07-06 09:40:23 +02:00
Kconfig	ChromeOS mainboards: Move more Kconfig symbols under CHROMEOS	2015-08-26 15:45:36 +00:00
Kconfig.name
mainboard.c	veyron_mickey: Apply differences between Brain and Mickey	2015-06-23 08:21:23 +02:00
Makefile.inc	google/veyron: Fix building with CHROMEOS enabled	2015-06-30 08:17:52 +02:00
memlayout.ld
reset.c
romstage.c	rk3288: Use timestamp region for pre-cbmem timestamps	2015-07-07 20:07:13 +02:00
sdram_configs.c	veyron: add Nanya NT5CC256M16DP sdram	2015-08-28 06:45:03 +00:00