coreboot-kgpe-d16/src/soc
Lin Huang 4ecccff72f rockchip/rk3399: set edp pclk to 25MHz
It may cause an edp aux transfer error if the edp pclk is
set too high, so reduce it to 25MHz.

BUG=chrome-os-partner:60130
BRANCH=None
TEST=Build and Boot

Change-Id: Id1063baa5a82637b03c0f1f754181df074ab17cc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8f7ce31a7483e765ae0c86f8e62ef51413ee1596
Original-Change-Id: Ibb86c12c1d7c00dc3b4cc7a6bdf3bd6e895cd9f3
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/429410
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18178
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-24 09:34:04 +01:00
..
broadcom/cygnus spi: Get rid of SPI_ATOMIC_SEQUENCING 2016-12-23 04:54:55 +01:00
dmp/vortex86ex src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-07-31 19:27:53 +02:00
imgtec/pistachio spi: Get rid of SPI_ATOMIC_SEQUENCING 2016-12-23 04:54:55 +01:00
intel soc/intel/skylake: Include I2C code in romstage 2017-01-22 19:24:37 +01:00
lowrisc/lowrisc soc/lowrisc: Place CBMEM at top of autodetected RAM 2016-12-06 18:51:13 +01:00
marvell soc/marvell/mvmap2315: Mark mvmap2315_reset() as noreturn 2017-01-12 18:52:11 +01:00
mediatek/mt8173 spi: Get rid of SPI_ATOMIC_SEQUENCING 2016-12-23 04:54:55 +01:00
nvidia spi: Define and use spi_ctrlr structure 2016-12-05 03:29:04 +01:00
qualcomm spi: Get rid of SPI_ATOMIC_SEQUENCING 2016-12-23 04:54:55 +01:00
rdc/r8610 rdc/r8610: Move to src/soc 2016-05-05 20:08:58 +02:00
rockchip rockchip/rk3399: set edp pclk to 25MHz 2017-01-24 09:34:04 +01:00
samsung samsung/exynos5420: Fix test for src < 0 2016-12-16 15:57:56 +01:00
ucb/riscv soc/ucb/riscv: Place CBMEM at top of autodetected RAM 2016-12-06 18:48:28 +01:00