4f012694dd
The 2nd COM port's base address defaults to 0x2f8. Current software for this system expects the port at 0x3e8. Configure COMB to use 0x3e8 instead of 0x2f8. BUG=N/A TEST=tested on facebook monolith Change-Id: Ibb462bad5f0594e0b5c8dea6e02cd42d58d999ab Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
32 lines
1.1 KiB
C
32 lines
1.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <device/pnp_ops.h>
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#include <device/pnp.h>
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#include "onboard.h"
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#define SERIAL_DEV1 PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */
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#define SERIAL_DEV2 PNP_DEV(ITE8528_CMD_PORT, 2) /* ITE8528 UART2 */
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void bootblock_mainboard_early_init(void)
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{
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/* Enable the serial ports inside the EC */
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pnp_set_logical_device(SERIAL_DEV1);
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pnp_set_enable(SERIAL_DEV1, 1);
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pnp_set_logical_device(SERIAL_DEV2);
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pnp_set_iobase(SERIAL_DEV2, PNP_IDX_IO0, 0x3e8);
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pnp_set_irq(SERIAL_DEV2, PNP_IDX_IRQ0, 3);
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pnp_set_enable(SERIAL_DEV2, 1);
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}
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