2019-12-05 13:45:41 +01:00
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/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <device/pnp_ops.h>
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2020-03-13 15:20:13 +01:00
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#include <device/pnp.h>
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2019-12-05 13:45:41 +01:00
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#include "onboard.h"
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2020-02-05 12:15:39 +01:00
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#define SERIAL_DEV1 PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */
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#define SERIAL_DEV2 PNP_DEV(ITE8528_CMD_PORT, 2) /* ITE8528 UART2 */
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2019-12-05 13:45:41 +01:00
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void bootblock_mainboard_early_init(void)
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{
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2020-02-05 12:15:39 +01:00
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/* Enable the serial ports inside the EC */
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pnp_set_logical_device(SERIAL_DEV1);
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pnp_set_enable(SERIAL_DEV1, 1);
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pnp_set_logical_device(SERIAL_DEV2);
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2020-03-13 15:20:13 +01:00
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pnp_set_iobase(SERIAL_DEV2, PNP_IDX_IO0, 0x3e8);
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pnp_set_irq(SERIAL_DEV2, PNP_IDX_IRQ0, 3);
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2020-02-05 12:15:39 +01:00
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pnp_set_enable(SERIAL_DEV2, 1);
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2019-12-05 13:45:41 +01:00
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}
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