505e383ccb
Commit 2c26108208 moved this function to
pmutil.c for Tiger Lake. Do this to all other platforms for consistency.
For Skylake, __SIMPLE_DEVICE__ preprocessor guards are no longer needed.
With this change, pmc.c is only needed in ramstage. Adjust Makefile.inc
accordingly, and drop ENV_RAMSTAGE guards from Skylake.
Change-Id: I424eb359c898f155659d085b888410b6bb58b9ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
110 lines
2.7 KiB
Makefile
110 lines
2.7 KiB
Makefile
ifeq ($(CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE),y)
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subdirs-y += nhlt
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subdirs-y += romstage
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subdirs-y += ../../../cpu/intel/common
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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bootblock-y += bootblock/bootblock.c
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bootblock-y += i2c.c
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bootblock-y += bootblock/pch.c
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bootblock-y += bootblock/report_platform.c
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bootblock-y += gpio.c
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bootblock-y += gspi.c
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bootblock-y += p2sb.c
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bootblock-y += pmutil.c
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bootblock-y += spi.c
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bootblock-y += lpc.c
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bootblock-y += uart.c
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verstage-y += gspi.c
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verstage-y += pmutil.c
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verstage-y += i2c.c
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verstage-y += spi.c
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verstage-y += uart.c
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romstage-y += gpio.c
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romstage-y += gspi.c
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romstage-y += i2c.c
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romstage-y += me.c
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romstage-y += pmutil.c
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romstage-y += reset.c
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romstage-y += spi.c
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romstage-y += uart.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += elog.c
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ramstage-y += fadt.c
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ramstage-y += finalize.c
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ramstage-y += gpio.c
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ramstage-y += gspi.c
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ramstage-y += i2c.c
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ramstage-y += graphics.c
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ramstage-y += irq.c
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ramstage-y += lockdown.c
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ramstage-y += lpc.c
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ramstage-y += me.c
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ramstage-y += p2sb.c
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ramstage-y += pmc.c
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ramstage-y += pmutil.c
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ramstage-y += reset.c
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ramstage-y += sd.c
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ramstage-y += spi.c
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ramstage-y += systemagent.c
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ramstage-y += uart.c
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ramstage-y += vr_config.c
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ramstage-y += xhci.c
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smm-y += elog.c
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smm-y += gpio.c
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smm-y += p2sb.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-y += uart.c
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smm-y += xhci.c
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postcar-y += gspi.c
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postcar-y += spi.c
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postcar-y += i2c.c
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postcar-y += uart.c
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ifeq ($(CONFIG_SKYLAKE_SOC_PCH_H),y)
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ifeq ($(CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU),y)
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# Skylake H Q0
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-5e-03
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endif
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ifeq ($(CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU),y)
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# Kabylake H B0 S0
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-09
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endif
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else
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ifeq ($(CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU),y)
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# Skylake D0
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-4e-03
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endif
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ifeq ($(CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_DUAL),y)
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# Kabylake H0, J0, J1
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-09
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endif
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ifeq ($(CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_QUAD),y)
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# Kabylake Y0
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0a
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endif
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endif
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# Missing for Skylake C0 (0x406e2), Kabylake G0 (0x406e8), Kabylake HA0 (0x506e8)
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# since those are probably pre-release samples.
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CPPFLAGS_common += -I$(src)/soc/intel/skylake
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CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
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# Currently used for microcode path.
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CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR)
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endif
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