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Martin Roth 510171e23b Tyan S8226: Fix integer truncated warning
Fix Warning:
  sb700_cfg.c:129, GNU Compiler 4 (gcc), Priority: Normal
  large integer implicitly truncated to unsigned type [-Woverflow]

The issue here was that an 8 bit value was being placed into a 2-bit
bitfield.

    $ more src/vendorcode/amd/cimx/sb700/SBTYPE.h
    […]
    UINT32  AzaliaSdin0     :2;                     //6
    UINT32  AzaliaSdin1     :2;                     //8
    UINT32  AzaliaSdin2     :2;                     //10
    UINT32  AzaliaSdin3     :2;                     //12
    $ more src/mainboard/tyan/s8226/sb700_cfg.h
    […]
     *  SDIN0 is define at BIT0 & BIT1
     *   00 - GPIO PIN
     *   01 - Reserved
     *   10 - As a Azalia SDIN pin
     *  SDIN1 is define at BIT2 & BIT3
     *  SDIN2 is define at BIT4 & BIT5
     *  SDIN3 is define at BIT6 & BIT7
     */
    #ifndef AZALIA_SDIN_PIN
    #define AZALIA_SDIN_PIN              0x2A
    #endif
    […]
    $ more src/mainboard/tyan/s8226/sb700_cfg.c
    […]
    	sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN;
    […]

The 8 bit value 0x2A (binary 00 10 10 10), was being used incorrectly
– I believe the original intent of this value was to enable the SDIN
pins 0, 1, & 2. Because it was getting truncated as it was put into
AzaliaSdin0, this wasn't happening and only SDIN0 was being enabled.

I am leaving only SDIN0 enabled at this point to as not change the
actual behavior on the platform.

Change-Id: Icaeb956926309dbfb5af25a36ccb842877e17a34
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2452
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-02-19 23:44:48 +01:00
3rdparty@dcd1ca72bb Update 3rdparty mark to latest repository 2013-02-11 21:51:05 +01:00
documentation sconfig: rename lapic_cluster -> cpu_cluster 2013-02-14 07:07:20 +01:00
payloads libpayload: libcbfs: Fix legacy CBFS API, typos 2013-02-19 19:44:57 +01:00
src Tyan S8226: Fix integer truncated warning 2013-02-19 23:44:48 +01:00
util romcc: Don't fail on function prototypes 2013-02-19 11:01:05 +01:00
.gitignore add a few entries to .gitignore 2013-01-10 22:51:20 +01:00
.gitmodules Add 3rdparty as submodule 2012-05-01 00:08:37 +02:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
Makefile build system: Retire REQUIRES_BLOB 2013-02-19 11:00:41 +01:00
Makefile.inc build system: Retire REQUIRES_BLOB 2013-02-19 11:00:41 +01:00
README Update README with newer version of the text from the web page 2011-06-15 10:16:33 +02:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.