Wonkyu Kim 528ae9e811 soc/tigerlake: Correct FSP log interface ... Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART. DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART BUG=None BRANCH=None TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39167 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-03-02 23:43:12 +00:00
..
acpi	src/acpi: Update license headers to SPDX	2020-01-02 14:49:00 +00:00
arch	x86/acpi_s3: Remove trailing dots from debug message	2020-03-02 15:08:52 +00:00
commonlib	lz4: Fix out-of-bounds reads	2020-03-02 15:03:03 +00:00
console	console/post: NOPOST means NOPOST	2020-01-18 10:53:08 +00:00
cpu	cpu/Kconfig: Remove old reference to ROMCC	2020-02-24 14:24:34 +00:00
device	device/Kconfig: select linear framebuffer for Tianocore	2020-02-24 13:10:47 +00:00
drivers	drivers/i2c/at24rf08c: Format according to coding style	2020-03-02 11:46:29 +00:00
ec	ec/google/chromeec: Introduce SKU_ID helpers	2020-02-28 00:02:35 +00:00
include	soc/intel/denverton: Move PCI IDs to pci_ids.h	2020-03-02 19:13:10 +00:00
lib	lib/lzma: Fix out-of-bounds read	2020-02-25 10:13:51 +00:00
mainboard	mb/google/kohaku: Add LPDDR 16G 2133 support	2020-03-02 11:53:06 +00:00
northbridge	nb/intel/sandybridge: Fix VBOOT	2020-03-02 11:49:03 +00:00
security	treewide: Capitalize 'CMOS'	2020-02-24 14:10:00 +00:00
soc	soc/tigerlake: Correct FSP log interface	2020-03-02 23:43:12 +00:00
southbridge	treewide: capitalize 'USB'	2020-02-26 17:06:40 +00:00
superio	superio/nuvoton/npcd378: Switch to superio/common	2020-03-02 10:19:44 +00:00
vendorcode	vendorcode/intel/fsp/fsp2_0: Add FSP header files for Skylake-SP	2020-03-02 11:44:47 +00:00
Kconfig	treewide: Capitalize 'CMOS'	2020-02-24 14:10:00 +00:00